Session 6A-2
Circuit Techniques to Improve Disturb
and Write Margin Degraded by MOSFET Variability
in High-Density SRAM Cells
| Device variability caused by continued technology scaling makes degradation of disturb and write margin a serious problem for high density SRAM cells. This paper reports the circuit techniques to cope with it, focusing on two topics: (1) Level Programmable Wordline Driver (LPWD) with Dynamic Array Supply Control (DASC) and (2) Constant-Negative Level Write Buffer (CNS-WB). Improvement of cell operation margin has been demonstrated by 40nm and 32nm test chips. |