Session 6B-1

High performance graphene FETs with self-aligned buried gates
fabricated on Scalable patterned Ni-Catalyzed Graphene

Abstract
For the first time, we report a scalable technique to fabricate graphene transistors with self-aligned buried gates process. The high performance buried-gate graphene transistor has excellent field effect mobility of 6,100 and 24,000 cm2 per volt second before and after subtraction of contact resistance. To the best of our knowledge, this is the highest room temperature mobility for CVD graphene FETs reported to date. This result paves the way for manufacturable high quality graphene transistor technology.