Session 8A-2

Yield and Reliability of 3DIC Technology
for Advanced 28nm Node and Beyond

 

Abstract

A stacked three-dimension integrated circuit (3D-IC) of 28nm chips was demonstrated. Key enabling technologies such as through silicon via (TSV) formation, wafer thinning, redistribution layer (RDL), micro bump and joint were developed for chip stacking and interconnect functions evaluation. The excellent performances of 3D-IC yield and reliability characteristics are key milestones in promising manufacturability of 3D-IC by silicon foundry technology.