Session 9A-4

Ultra Thin Buried Nitride Integration
for Multi-V_T, low Variability and Power
Management in Planar FDSOI CMOFETs

Abstract

We highlight an original solution to adjust the threshold voltage of Fully Depleted Silicon-On-Insulator CMOS down to 20nm gate length thanks to charge storage in a thin buried nitride layer. In particular, high performance pMOS with Ioff=500nA/micron (VT=-0.2V) are demonstrated in a gate first approach. This technique is combined with back-bias for power management and with a smart processcompensation technique to improve the device variability down to sigma(VT)=4mV for L=30nm and W=500nm.