Session 9B-2
Ultra-Low Leakage Junction Engineering
of Cell Transistor by Raised Source/Drain
for Logic-Compatible 28-nm Embedded DRAM
| An ultra-low leakage junction design concept is proposed for further scaling of cell transistor for logic-compatible eDRAM. Raised source/drain (RSD) enables to introduce graded junction to short-channel FET to reduce junction leakage. Furthermore, the LDD formed by thermal diffusion from phosphorus-doped RSD enables to suppress subthreshold leakage by removing LDD ion implantation that causes extra junction broadening. We demonstrated the cell FET with 0.1-pA off-leakage at 115C without Ion degradation for fully logic-compatible 28-nm eDRAM. |