Session 9B-3

Offset Buried Metal Gate Vertical Floating Body Memory Technology
with Excellent Retention Time for DRAM Application

 

Abstract

Offset buried metal gate vertical floating body (FB) memory cell technology fabricated on a recess gate DRAM technology is presented. Cell operating window (OW) is improved by 75%, while static and disturb tRET @ 1.3V, T=93C are > 10x better than our previous work [1]. Array measurements and TCAD results confirm that maximum junction electric field (Emax) reduction is the primary reason for tRET improvement.