JOINT TECHNOLOGY/CIRCUITS RUMP SESSION

Tuesday, June 12

8:00 p.m. – 10:00 p.m.

Organizers:

Circuits

N. Lu, Etron

M. Bauer, Micron

Technology

T. Skotnicki, STMicroelectronics

K. Miyashita, Toshiba

RJ1: Scaling Challenges Beyond 1x nm DRAM and NAND Flash

Moderator: N. Lu, Etron

R. Shrivastava, SanDisk

The combined revenues of DRAM and NAND Flash approached $54 Billion in 2010. This is expected to continue to grow in the coming years. Emerging silicon and package technologies will further drive lower cost and new applications. The difficulty of scaling and developing new technologies and investments to build new factories is increasing at about the same rate as the memory bit growth in the world. At the same time, the industry is becoming aware that we are closing in on physical and electrical scaling limitations. As we close in on scaling limits, the use of new materials, manufacturing processes, and circuit design will become unavoidable. To compound the problem, fierce competition is forcing shorter development times. Our industry needs to openly address these issues and challenges in order to continue developing better and lower cost memories for the decade to come. The whole industry faces these challenges and issues. They are huge. We have assembled a representative group of industry experts for this Joint Rump Session. We will ask them to discuss the top issues from the perspective of each one’s area of expertise. The floor will be open to question the panelist's view or challenge them to consider issues that audience would like to raise.

Panelists:

G. Atwood, Micron

G. Bronner, Rambus

C.Y. Lu, Macronix

K. Takeuchi, University of Tokyo

S. Aritome, Hynix

H. Hazama, Toshiba

M. Koyanagi, Tohoku Univ.

H-K Kang, Samsung