Session 10 – TAPA I

Wireless Connectivity and Software Defined Radios

Thursday, June 14, 10:00 a.m.

Chairpersons: B. Ginsberg, Texas Instruments

H. Ishikuro, Keio University

10.1 - 10:00 a.m.

A -70dBm-Sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX Transceiver for TransferJet^TM SoC in 65nm CMOS, D. Miyashita, K.Agawa, H. Kajihara, K. Sami, M. Iwanaga, Y. Ogasawara, T. Ito, D. Kurose, N. Koide, T. Hashimoto, H. Sakurai, T. Yamaji, T. Kurihara, K.Sato, I. Seto, H. Yoshid, R. Fujimoto, Y. Unikawa, Toshiba Corp.

TransferJet(TM) is an emerging high-speed close-proximity wireless communication standard, which enables a data transfer of up to 522Mbps within a few centimeters range. We have developed a fully integrated TransferJet SoC with a 4.48-GHz operating frequency and a 560-MHz bandwidth (BW) using 65nm CMOS technology. Baseband filtering techniques for both a transmitter (TX) and a receiver (RX) are proposed to obtain a sensitivity of -70dBm with low power consumption. The SoC achieves an energy per bit of 0.19nJ/bit and 0.43nJ/bit for the TX and the RX, respectively, We have also built the world’s smallest module prototype using the SoC, which is suitable for small mobile devices.

10.2 - 10:25 a.m.

A 2.4GHz WLAN Transceiver with Fully-integrated Highly-linear 1.8V 28.4dBm PA, 34dBm T/R Switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS, Y. Tan, J. Duster, C.-t. Fu, E. Alpman, A. Balankutty, C.C. Lee, A. Ravi, S. Pellerano, K. Chandrashekar, H. S. Kim, B. Carlton, S. Suzuki, M. Shafi, Y. Palaskas, H. Lakdawala, Intel Corporation

A 2.4GHz WLAN transceiver is presented with a fully-integrated highly-linear 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC and 320MS/s ADC (high OSR for relaxed filtering), DPLL and fractional LOG, in 32nm CMOS. For 802.11g 54Mbps, without linearization the TX delivers 19.8dBm at 12.5% efficiency (PA 21.6dBm/19.7% PAE) for -25dB EVM and mask-compliant 22.8dBm/18.5%, while the RX achieves 4.8dB NF, -69dBm sensitivity, and -8dBm IIP3.

10.3 - 10:50 a.m.

A +30.5 dBm CMOS Doherty Power Amplifier with Reliability Enhancement Technique, K.Onizuka, S. Saigusa, S.Otaka, Toshiba Corporation

A watt-level, fully integrated 1:1 Doherty power amplifier for 2.4 GHz band is demonstrated in 65 nm CMOS. Both high peak output power of +30.5 dBm and high PAE of 23% at 6 dB power back-off are achieved by the proposed compact output network. A newly introduced reliability enhancement technique for sub-PA prolongs time to failure by up to 75% as well. The PA satisfies IEEE 802.11b and 11g spectrum masks at output power levels of 25.5 and 21.5 dBm respectively, from supply voltage of 3.3 V.

10.4 - 11:15 a.m.

A Harmonic-Rejecting CMOS LNA for Broadband Radios, J.W. Park, B. Razavi, University of California, Los Angeles

A feedback LNA employs programmable notch filtering so as to suppress by 20 dB blockers at LO harmonics from 300 MHz to 10 GHz. Fabricated in 65-nm technology, the LNA exhibits a noise figure of less than 3 dB from 300 MHz to 4 GHz while consuming 8.6 mW from a 1.2-V supply.

10.5 - 11:40 a.m.

A 13.5mA Sub-2.5dB NF Multi-Band Receiver, M. Mikhemar, A. Mirzaei, A. Hadji-Abdolhamid, J. Chiu, H. Darabi, Broadcom Corporation

An ultra low-power multi-band receiver covering any frequency band in the range 0.7-2.5GHz is fabricated in 40nm CMOS and occupies a total area of 1.5mm2. The receiver achieves a NF of 2.4dB, with -2dBm IIP3, and a peak SNR of 35dB, while consuming 13.5mA from the battery, more than three times power reduction compared to prior art.