Session 11 – Honolulu Suite

Successive Approximation A/D Converters

Thursday, June 14, 10:00 a.m.

Chairpersons: M. Flynn, University of Michigan

S. Dosho, Panasonic Corp.

11.1 - 10:00 a.m.

A 2.8GS/s 44.6mW Time-Interleaved ADC Achieving 50.9dB SNDR and 3dB Effective Resolution Bandwidth of 1.5GHz in 65nm CMOS, D. Stepanovic, B. Nikolic, University of California, Berkeley

This paper presents a power- and area-efficient 24-way time-interleaved SAR ADC designed in 65nm CMOS. At 2.8GS/s sampling rate the ADC consumes 44.6mW of power from a 1.2V supply while achieving peak SNDR of 50.9dB and retaining SNDR higher than 48.2dB across the entire first Nyquist zone.

11.2 - 10:25 a.m.

A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure, C.-H. Chan, Y. Zhu, S.-W. Sin, S.-P. U, R. Martins*, University of Macau, *TU of Lisbon

An 8b 1GS/s ADC is presented that interleaves two 2b/cycle SARs. To enhance speed and save power, the prototype utilizes segmentation switching and custom-designed DAC array with high density in a low parasitic layout structure. It operates at 1GS/s from 1V supply without interleaving calibration and consumes 3.8mW of power, exhibiting a FoM of 24fJ/conversion step. The ADC occupies an active area of 0.013mm^2 in 65nm CMOS including on-chip offset

calibration.

11.3 - 10:50 a.m.

A 4.5-mW 8-b 750-MS/s 2-b/Step Asynchronous Subranged SAR ADC in 28-nm CMOS Technology, Y.-C. Lien, MediaTek

A 8-b 2-b/step asynchronous subranged SAR ADC is presented. It incorporates subranging technique to obtain fast reference settling for MSB conversion. The capacitive interpolation reduces number of NMOS switches and lowers matching requirement of a resistive DAC. The proposed timing scheme avoids the need of specific duty cycle of external clock for defining sampling period in a conventional asynchronous SAR ADC. Operating at 750 MS/s, this ADC consumes 4.5 mW from 1-V supply, achieves ENOB of 7.2 and FOM of 41 fJ/conversion-step. It is fabricated in 28-nm CMOS technology and occupies an active area of only 40 um X 100 um.

11.4 - 11:15 a.m.

A 34fJ 10b 500 MS/s Partial-Interleaving Pipelined SAR ADC, Y. Zhu, C.-H. Chan, S.-W. Sin, S.-P. U, R. Martins*, University of Macau, *TU of Lisbon

A 10b 500MS/s ADC is presented that shares a full-speed SAR at front-end and interleaves the pipelined residue amplification with shared opamp and 2nd-stage SAR ADCs, which achieves high speed, low power and compact area. The prototype ADC in 65nm CMOS achieves a mean SNDR of 55.4dB with 8.2mW power dissipation at 1.2V. The active die area including the offset calibrations is 0.046mm^2.

11.5 - 11:40 a.m.

A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS, H.-Y. Tai, H.-W. Chen, H.-S. Chen, National Taiwan University

A low-voltage energy-efficient SAR ADC is presented in this paper with four techniques. Arbitrary weight capacitor array tolerates errors to reduce conversion time. To operate under low voltage, DAC common mode level shift and leakage reduction sample switch with a charge pump are proposed. Differential control logic is used to save its digital power. The prototype ADC consumes 170nW at 100KS/s from a 0.35V supply. It achieves an SNDR of 56.3dB at Nyquist rate and its FOM is 3.2fJ/c.-s.