CIRCUITS SESSION 12 – Tapa 1

Technology/Circuits Joint Focus Session - Design Enablement in Scaled CMOS

Thursday, June 14, 1:30 p.m.

Chairpersons: K. Wilcox, AMD

K. Nose, Renesas Electronics Corp.

12.1 - 1:30 p.m.

A 22nm Dynamically Adaptive Clock Distribution for Voltage Droop Tolerance, K. Bowman, C. Tokunaga, T. Karnik, V. De, J. Tschanz, Intel

An all-digital dynamically adaptive clock distribution mitigates the impact of high-frequency supply voltage (Vcc) droops on microprocessor performance and energy efficiency. Silicon measurements from a test chip in a 22nm tri-gate technology demonstrate simultaneous throughput gains and energy reductions ranging from 14% and 3% at 1.0V to 31% and 15% at 0.6V, respectively, for a 10% Vcc droop.

12.2 - 1:55 p.m.

Voltage Droop Reduction Using Throttling Controlled by Timing Margin Feedback, M. Floyd, A. Drake*, R. Berry, H. Chase, R. Willaman, J. Pena, IBM System and Technology Group, *IBM Austin Research Lab

An active processor throttling control loop was enabled in the shipping POWER7™ based P775 supercomputer to mitigate voltage droop. Critical path measurement circuits built into the POWER7 processor chips are used to dynamically measure and react to loss of timing margin. This technique was used to save power without dropping frequency and to only engage if a worst-case droop event occurred in the system. As a result, worst-case workload-induced voltage droop events are reduced by around 50% compared to the system operating without the control loop. The reduction in operating voltage afforded by this technique translates to significant yield improvement, reduced failure rates (around 60% FIT reduction), and improved power efficiency (32W per processor chip, which translates into more than $600 per node per year, which is well more than $250,000 per year in a proposed 512 node installation).

12.3 - 2:20 p.m.

An On-Die All-Digital Delay Measurement Circuit with 250fs Accuracy, M. Mansuri, B. Casper, F. O'Mahony, Intel Corporation

This paper demonstrates an in-situ delay measurement circuit which precisely characterizes key clocking circuits such as full phase rotation interpolators. This on-die all-digital circuit produces a digital output value proportional to the relative delay between two clocks, normalized to the clock period. This circuit requires no calibration for variation or process, voltage, temperature (PVT) and measures the delay with 250fs absolute accuracy and repeatability of 10fs-rms.

12.4 - 2:45 p.m.

A 47% Access Time Reduction with a Worst-Case Timing-Generation Scheme Utilizing a Statistical Method for Ultra Low Voltage SRAMs, A. Kawasumi, Y. Takeyama, O. Hirabayashi, K. Kushida, F. Tachibana, Y. Niki, S. Sasaki, T. Yabe, Toshiba

A variation tolerant sense amplifier timing generator which utilizes a statistical method is proposed. The circuit monitors all the bitline delays and generates the worst timing from the delay distribution. The timing generating circuits have been implemented in 28nm and 40nm SRAMs. The 47% access time improvement at 0.5V has been confirmed in measured results.