Session 13 – Honolulu Suite

High Performance Transceivers

Thursday, June 14, 1:30 p.m.

Chairpersons: J. Zerbe, Rambus

J. Terada, NTT Microsystem Integration Labs

13.1 - 1:30 p.m.

A 3.1mW/Gbps 30Gbps Quarter-Rate Triple-Speculation 15-tap SC-DFE RX Data Path in 32nm CMOS, T. Toifl, M. Ruegg*, R. Inti**, C. Menolfi, M. Brändli, M. Kossel, P. Buchmann, P.A. Francese, T. Morf, IBM Research GmbH, *Miromico, **Oregon State University

This paper describes a low-power implementation of a receiver data path, consisting of the RX termination with ESD, continuous-time linear equalizer (CTLE), and a 15-tap decision feedback equalizer (DFE) running at quarter rate. While the first 3 DFE taps are implemented by speculation, the latter 12 taps use a switched-cap (SC-DFE) approach. The circuit was produced in 32nm SOI-CMOS, and was measured to receive 30Gb/s PRBS31 data at <10-12 BER over a 36dB loss channel with an energy efficiency of 3.1mW/Gbps.

13.2 - 1:55 p.m.

A Wide Common-Mode Fully-Adaptive Multi-Standard 12.5Gb/s Backplane Transceiver in 28nm CMOS, J. Savoj, K. Hsieh, P. Upadhyaya, F.-T. An, A. Bekele, S. Chen, X. Jiang, K.W. Lai, C.F. Poon, A. Sewani, D. Turker, K. Venna, D. Wu, B. Xu, E. Alon*, K. Chang, Xilinx, Inc., *University of California, Berkeley

This paper describes the design of a fully-adaptive backplane transceiver embedded in a state-of-the-art, low-leakage, 28nm CMOS FPGA. The wide common mode receive AFE utilizes a three-stage CTLE to provide selective frequency boost for long-tail ISI cancellation. A 5-tap speculative DFE removes the immediate post-cursor ISI. Both CTLE and DFE are fully adaptive using sign-sign LMS algorithm. A novel clocking technique uses wideband LC and ring oscillators for reliable clocking from 0.6-12.5Gb/s operation. The transmitter utilizes a 3-tap FIR and provides flexibility for supply and ground referenced operation. The transceiver achieves BER < 10^-15 over a 33dB-loss backplane at 12.5Gb/s and over multiple channels with 10G-KR characteristics at 10.3125Gb/s.

13.3 - 2:20 p.m.

A 25-Gb/s 2.2-W Optical Transceiver Using an Analog FE Tolerant to Power Supply Noise and Redundant Data Format Conversion in 65-nm CMOS, T. Takemoto, H. Yamashita, T. Kamimura, F. Yuki, N. Masuda, H. Toyoda, N. Chujo, K. Kogo, Y. Lee, S. Tsuji, S. Nishimura, Hitachi, Ltd.

A one-chip optical transceiver was developed for backplane transmission inside ICT systems by integrating an analog FE with data format conversion (DFC) in 65-nm CMOS. 10 × 6.25-Gb/s electrical signals were converted into 4 × 25-Gb/s optical signals with 25% redundancy to improve resilience against the possible failure of laser diodes (LD). A TIA with a noise canceller and fully differential LD driver (LDD) with two-tap de-emphasis were proposed for achieving tolerance to power supply noise. The noise canceller suppressed power-supply variations by 98% compared to our previous TIA. Moreover, the integrated redundant DFC improved transceiver reliability without relying on redundant network topologies at the system level. Total power consumption at full channel operation was only 2.2 W, including 236 and 831 mW for the TIA and LDD with power efficiencies of 2.4 and 8.3 mW/Gb/s, respectively.

13.4 - 2:45 p.m.

A 100+ meter 12Gb/s/Lane Copper Cable Link Based on Clock-Forwarding, T. Ali, W.H. Park, P. Mulage, E.-H. Chen, R. Ho*, C.-K.K. Yang, UCLA, *Oracle Labs

Active and passive copper cables for data rates exceeding 10Gb/s are typically limited to less than 20m. Optical fiber on the other hand offers superior performance for run length greater than 100m, but is costly and has large power requirements exceeding 1W per link. Although 100m copper link is demonstrated for 10GBASE-T, it utilizes complex symbols at a lower symbol rate and dissipates large power for DSP. In this paper we propose a 12Gbps/lane active cable link that extends copper cables >100 meters using low power and area repeaters powered through the cable that can potentially be embedded in the cable. An FIR filtering technique, and a low-jitter configurable PLL/MDLL enables the delivery of a low jitter forward clock along the entire cable. Total jitter at the end of the cable is 4.4ps RMS. The link at each repeater occupies 0.095mm2 of area in a 65nm technology dissipating 48mW.