Session 16 – TAPA I

Circuits Special Focus Session - Flash Memory

Friday, June 15, 8:05 a.m.

Chairpersons: M. Bauer, Micron Tech.

H. Hwang, Samsung Electronics Co., Ltd.

16.1 - 8:05am

A Logic-Compatible Embedded Flash Memory Featuring a Multi-Story High Voltage Switch and a Selective Refresh Scheme, S.-H. Song, K.C. Chun, C.H. Kim, University of Minnesota

A logic-compatible embedded flash memory that uses no special devices other than standard core and IO transistors is demonstrated in a low-power standard logic process having a 5nm tunnel oxide. An overstress-free high voltage switch expands the cell VTH window by >170% while a 5T embedded flash memory cell with a selective row refresh scheme is employed for improved endurance.

16.2 - 8:30 a.m.

A New 3-bit Programming Algorithm using SLC-to-TLC Migration for 8MB/s High Performance TLC NAND Flash Memory, S.-h. Shin, D.-K. Shim, J.-Y. Jeong, O.-S. Kwon, S.-Y. Yoon, M.-H. Choi, T.-Y. Kim, H.-W. Park, H.-J. Yoon, Y.-S. Song, Y.-H. Choi, S.-W. Shim, Y.-L. Ahn, K.-T. Park, J.-M. Han, K.-H. Kyung, Y.-H. Jun, Samsung Electronics

We have developed a new 3-bit programming algorithm of high performance TLC(Triple-level-cell, 3-bit/cell) NAND flash memories for 20nm node and beyond. By using the proposed 3-bit algorithm based on reprogramming with SLC-to-TLC migration, performance and BER is improved by 50% and 68%, respectively, compared to conventional method. The proposed algorithm is successfully implemented in 21nm 64Gb TLC NAND flash product that provides 8MB/s write and 400MB/s read throughputs.

16.3 - 8:55 a.m.

x11 Performance Increase, x6.9 Endurance Enhancement, 93% Energy Reduction of 3D TSV-Integrated Hybrid ReRAM/MLC NAND SSDs by Data Fragmentation Suppression, H. Fujii, K. Miyaji, K. Johguchi, K. Higuchi, C. Sun, K. Takeuchi, University of Tokyo

A 3D through-silicon-via (TSV) -integrated hybrid ReRAM/multi-level-cell (MLC) NAND solid-state drives (SSDs) architecture is proposed for PC, server and smart phone applications. NAND-like interface and sector-access overwrite policy are proposed for the ReRAM. Furthermore, three intelligent data management algorithms (anti-fragmentation, most-recently-used and reconsidered-as-a-fragmentation algorithms) are proposed. The proposed algorithms suppress data fragmentation and excess usage of the MLC NAND by storing hot data in the ReRAM. As a result, 11 times performance increase, 6.9 times endurance enhancement and 93% write energy reduction are achieved compared with the conventional MLC NAND SSD. Both ReRAM write and read latency should be less than 3us to obtain these improvements. The Required endurance for ReRAM is 1e5. 3D TSV interconnects reduce the energy consumption by

68%.

16.4 - 9:20 a.m.

Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH, Y.S. Cho, I.H. Park, S.Y. Yoon, N.H. Lee, S.H. Joo, K.-W. Song, K. Choi, J.M. Han, K.H. Kyung, Y.-H. Jun, Samsung Electronics Co., Ltd.

As device technology is scaling down, Vth’s of flash cell show wide distribution due to process variation such as random dopant fluctuation, etc. Since the extension of Vth distribution is directly related with the performance degradation of NAND flash, it is more challenging to make a high performance flash memory. This paper presents a novel program scheme, called Adaptive Multi-pulse Program (AMP), which targets toward scaled multi-bit/cell NAND flash devices. In the AMP scheme memory cells are divided into several groups based on its own program speed. Suitable program voltages are applied for each group and thus cells having different program speed reach its target level at the same time. Our experimental results show that AMP achieves ~20% improvement on program performance in 3-bit/cell architecture of 21nm CMOS technology.