Session 17 – TAPA II

Low Power Receivers and Jitter Reduction

Friday, June 15, 8:05 a.m.

Chairpersons: K. Chang, Xilinx

C. Yoo, Hanyang University

17.1 - 8:05 a.m.

A 25-Gb/s 5-mW CMOS CDR/Deserializer, J.W. Jung, B. Razavi, University of California, Los Angeles

A half-rate clock and data recovery circuit and a deserializer employ charge-steering logic to reduce the power consumption. Realized in 65-nm technology, the overall circuit draws 5 mW from a 1-V supply, producing a clock with an rms jitter of 1.5 ps and a jitter tolerance of 0.5 UIpp at 5 MHz.

17.2 - 8:30 a.m.

4×12 Gb/s 0.96 pJ/b/lane Analog-IIR Crosstalk Cancellation and Signal Reutilization Receiver for Single-Ended I/Os in 65 nm CMOS, T. Oh, R. Harjani, University of Minnesota

A crosstalk cancellation and signal reutilization (XTCR) algorithm implemented with analog-IIR networks dramatically improves signal integrity across 4 closely-spaced single-ended PCB traces. The prototype XTCR design implemented in 65 nm CMOS improves the measured average horizontal and vertical-eye openings of the 4 channels by 37.5% and 26.4% at 10-8 BER, while consuming only 0.96 pJ/b/lane.

17.3 - 8:55 a.m.

A Clock Jitter Reduction Circuit Using Gated Phase Blending Between Self-Delayed Clock Edges, K. Niitsu, N. Harigai, D. Hirabayashi, D. Oki, M. Sakurai, O. Kobayashi*, T.J. Yamaguchi, H. Kobayashi, Gunma University, *STARC

A clock jitter reduction circuit is presented that exploits the phase blending technique between the uncorrelated clock edges that are self-delayed by multiples of the clock cycle, nT. By blending non-correlated clock edges, the output clock edges approach the ideal timing and, thus, timing jitter can be reduced by a factor of the square root of two per stage. There are three technical challenges to realize this: 1) generating non-correlated clock edges, 2) phase averaging with small time offset from the ideal center position, and 3) minimizing the error in nT-delay being deviated from ideal nT. The proposed circuit overcomes each of these by exploiting an nT-delay, gated phase blending, and self-calibrated nT-delay elements, respectively. Measurement results with a 180-nm CMOS prototype chip demonstrated an approximately four-fold reduction in timing jitter from 30.2ps to 8.8ps in 500-MHz clock by cascading the proposed circuit with four-stages.

17.4 - 9:20 a.m.

A 1.22mW/Gb/s 9.6Gb/s Data Jitter Mixing Forwarded-Clock Receiver Robust against Power Noise with 1.92ns Latency Mismatch between Data and Clock in 65nm CMOS, S.-H. Chung, L.-S. Kim, KAIST

This paper presents a data jitter mixing forwarded-clock receiver which is robust against power supply induced jitter (PSIJ) and overcomes 1.92ns latency mismatch between data and clock. The forwarded-clock architecture has a tradeoff between the number of clock channels and the achievable data rate due to the lack of the jitter correlation between data and clock. Moreover, PSIJ due to a long clock distribution network and an injection-locked oscillator reduces the jitter correlation further. The proposed receiver eases this tradeoff, and also increases the jitter correlation reduced by PSIJ. The test chip achieves 9.6Gb/s with 1.22mW/Gb/s and occupies only 0.017mm2 in 65nm CMOS.