Session 18 – TAPA I

SoC and Signal Processors

Friday, June 15, 10:00 a.m.

Chairpersons: E. Yeo, Marvell Semiconductors

M. Motomura, Hokkaido University

18.1 - 10:00 a.m.

A Low Power Many-Core SoC with Two 32-Core Clusters Connected by Tree Based NoC for Multimedia Applications, H. Xu, J. Tanabe, H. Usui, S. Hosoda, T. Sano, K. Yamamoto, T. Kodaka, N. Nonogaki, N. Ozaki, T. Miyamori, Toshiba Corporation

A low-power many-core SoC for multimedia applications is implemented in 40nm CMOS technology. Within a 209.3mm2 die, two 32-core clusters are integrated with dynamically reconfigurable processors, hardware accelerators, 2-channel DDR3 I/Fs, and other peripherals. Processor cores in the cluster share a 2MB L2 cache connected through a tree-based Network-on-Chip (NoC). The high scalability and low power consumption is accomplished by　the parallelized firmware for multimedia applications, such as the H.264 1080p 30fps decoding under 500mW and the super resolution 4K2K 15fps image processing under 800mW.

18.2 - 10:25 a.m.

A 69mW 140-meter/60fps and 60-meter/300fps Intelligent Vision SoC for Versatile Automotive Applications, Y.-M. Tsai, T.-J. Yang, C.-C. Tsai, K.-Y. Huang, L.-G. Chen, National Taiwan University

A machine-learning based intelligent vision SoC implemented on a 9.3 mm2 die in a 40nm CMOS process is presented. The architecture realizes 140 meters active distance at 60fps and 60 meters at 300fps under Quad-VGA (1280×960) resolution while maintaining above 90% detec-tion rate for versatile automotive applications. The system supports 64 object tracking and prediction. It raises 1.62× improvement on power efficiency and at least 1.79× increase on frame rate with the proposed knowledge-based tracking processor. The chip achieves 354.2fps/W and 3.01TOPS/W power efficiency with 69mW average power consumption.

18.3 - 10:50 a.m.

A 4320p 60fps H.264/AVC Intra-Frame Encoder Chip with 1.41Gbins/s CABAC, D. Zhou, G. He, W. Fei, Z. Chen, J. Zhou, S. Goto, Waseda University

An H.264/AVC intra-frame video encoder is implemented in 65nm CMOS. With an efficient intra prediction design, its maximum throughput reaches 1991Mpixels/s for 7680x4320p 60fps video, 9.4x to 32x faster than previous designs. The encoder also incorporates a 1.41Gbins/s CABAC architecture that has been enhanced by 31%. Moreover, low energy consumption is achieved by the high parallelism and hardware efficiency of this design. 1080p30 encoding dissipates only 2mW at 0.8V and 9MHz.

18.4 - 11:15 a.m.

A Sub-100μW Multi-Functional Cardiac Signal Processor for Mobile Healthcare Applications, S.-Y. Hsu, Y. Ho, Y. Tseng, T.-Y. Lin, P.-Y. Chang, J.-W. Lee, J.-H. Hsiao, S.-M. Chuang, T.-Z. Yang*, P.-C. Liu, T.-F. Yang, R.-J. Chen**, C. Su, C.-Y. Lee, National Chiao Tung University, *Taipei Medical University Hospital, **Wan Fang Hospital

A multi-functional cardiac signal processor (CSP) with integrated sensor interfaces is designed for mobile healthcare applications, especially for heart activity diagnosis in different phases. Applying dedicated processing engines, the CSP extracts critical cardiac signal features based on compressed data with 90% storage reduction, while keeping the data network secure. Implemented in 90nm CMOS, the CSP consumes 22.6-46.5μW at 0.5/1.0V in different configurations. Besides, the 10.2μW biopotential and 11.4μW capacitive sensor interfaces further enhance the system functionality.

18.5 - 11:40 a.m.

A 0.25V 460nW Asynchronous Neural Signal Processor with Inherent Leakage Suppression, T.-T. Liu, J. Rabaey, University of California, Berkeley

A neural signal processor exploits an asynchronous timing strategy to dynamically minimize leakage and to self-adapt to the process variations and different operating conditions. Based on a logic topology with built-in leakage suppression, the self-timed processor demonstrates robust sub-threshold operation down to 0.25V, while consuming only 460nW in 0.03mm2 in a 65nm CMOS technology, representing a 4.4X reduction in power compared to the state-of-the-art designs.