Session 19 – TAPA II

∆∑ Converters

Friday, June 15, 10:00 a.m.

Chairpersons: I. Fujimori, Broadcom Corp.

M. Yoshioka, Fujitsu Labs, Ltd.

19.1 - 10:00 a.m.

A 10 MHz BW 50 fJ/conv. Continuous Time ∆∑ Modulator with High-order Single Opamp Integrator using Optimization-based Design Method, K. Matsukawa, K. Obata, Y. Mitani, S. Dosho, Panasonic Corporation

We propose not only new power and area efficient circuit configurations but also an optimization design method for such configurations. So far, design difficulties of the modulator, such as a trade-off between loop stability and a performance and unknown distortion mechanism, have been serious obstacles to improve the efficiency. Major factors to overcome these obstacles are new high-order single opamp integrators using optimization-based design method and tuning systems for harmonic distortions. Two design examples for TV-tuner application confirm that those design approach can maximize the performance of various types of modulators. A simple 3rd-order modulator achieved the FOM of 101 fJ/conv. and more complex 4th-order one achieved 50 fJ/conv. which is less than half of ever reported.

19.2 - 10:25 a.m.

A 5MHz BW 70.7dB SNDR Noise-Shaped Two-Step Quantizer Based ΔƩ ADC, T. Oh, N. Maghari*, U.-K.Moon, Oregon State University, *University of Florida

In this paper, a new ΔƩ ADC using a noise-shaped two-step integrating quantizer is presented. Attaining an extra order of noise-shaping from the integrating quantizer, the proposed ΔƩ ADC manifests a second-order noise-shaping with a first-order loop filter. Furthermore, this quantizer provides an 8b quantization in itself, drastically reducing the oversampling requirement. The proposed ADC also incorporates a new feedback DAC topology that alleviates feedback DAC complexity of a two-step 8b quantizer. The measured results of the prototype ADC implemented in a 0.13µm CMOS demonstrate peak SNDR of 70.7dB at 8.1mW power, with an 8x OSR at 80MHz sampling frequency.

19.3 - 10:50 a.m.

An 85dB SFDR 67dB SNDR 8OSR 240MS/s ∑∆ ADC with Nonlinear Memory Error Calibration, S.-C. Lee, B. Elies*, Y. Chiu*, University of Illinois at Urbana-Champagne, *University of Texas at Dallas

A 1-0 MASH sigma-delta ADC demonstrates a digital calibration technique treating both amplifier distortion and capacitor mismatch. The output-referred error analysis accurately models a nonlinear modulator. The identification of multiple error parameters is accomplished by correlating various moments of the ADC output with a one-bit pseudorandom noise (PN). The prototype ADC employing 29dB gain amplifiers measures 85dB SFDR and 67dB SNDR for a-1dBFS (1.1Vpp) 5MHz sinusoidal input at 240MS/s. The core ADC consumes 37mW from a 1.25V supply and occupies 0.28mm2 in a 65nm CMOS low-leakage digital process, in which the transistor threshold voltages are around 0.5V.

19.4 - 11:15 a.m.

A Reconfigurable Mostly-Digital ΔΣ ADC with a Worst-Case FOM of 160dB, G. Taylor, I. Galton*, Analog Devices, *University of California at San Diego

This paper presents a mostly-digital background-calibrated delta-sigma modulator ADC based on voltage-controlled ring oscillators (VCROs). As a result of several new techniques its performance is in line with the best delta-sigma modulators published to date, but it occupies much less circuit area and unlike other high-performance ADCs it is reconfigurable and consists mainly of digital circuitry. It does not use op-amps, analog integrators, feedback DACs, comparators, or reference voltages, so its performance is set by the speed of its digital circuitry and its supply voltage can be scaled with its sample-rate to save power. The sample rate is is tunable from 1.3-2.4GHz over which the SNDR spans 70-75dB, the bandwidth spans 5-37.5MHz, and the minimum SNDR + 10log(bandwidth/power dissipation) figure of merit (FOM) is 160dB. The 65nm CMOS delta-sigma modulator occupies 0.075 square millimeters and operates from

a single 0.9-1.2V supply.

19.5 - 11:40 a.m.

A 71dB Dynamic Range Third-Order ΔΣ TDC Using Charge-Pump, M. Gande, N. Maghari*, T. Oh, U.-K. Moon, Oregon State University, *University of Florida

A high resolution time-to-digital converter (TDC) architecture is proposed. The architecture combines the principles of noise-shaping quantization and charge-pump to build a third-order ΔΣ TDC with a dedicated feedback DAC. Fabricated in a 0.13µm CMOS process, the prototype TDC achieves better than 71dB DR and 67dB SNDR in 2.81MHz signal bandwidth (OSR=16) and consumes 2.58mW.