Session 2 – TAPA I

Phase Locked Loops and Oscillators

Wednesday, June 13, 10:05 a.m

Chairpersons: B. Nauta, University of Twente

S. Cho, KAIST

2.1 - 10:25 a.m.

Components for Generating and Phase Locking 390-GHz Signal in 45-nm CMOS, D. Shim#, D. Koukis, D. Arenas, D. Tanner, E. Seok*, J. Brewer, K. O**, #University of Florida and Seoul National University of Scince and Technology, *Texas Instruments, **University of Texas at Dallas

Components for generating and phase locking 390-GHz signal are demonstrated using low leakage transistors in 45-nm CMOS. An integrated chain of circuits composed of an 195-GHz oscillator with frequency doubled output at ~390 GHz followed by two cascaded divide-by-two injection locked frequency dividers with output frequency of ~49 GHz is demonstrated. The peak power radiated at ~390 GHz by an on-chip antenna is ~2 uW. The oscillator and frequency divider consumes 21 and 6 mW, respectively.

2.2 - 10:50 a.m.

A 160-GHz Receiver-Based Phase-Locked Loop in 65 nm CMOS Technology, W.-Z. Chen, T.-Y. Lu, Y.-T. Wang, J.-T. Jian, Y.-H. Yang, G.-W. Huang*, W.-D. Liu*, C.-H. Hsiao*, S.-Y. Lin*, J.Y. Liao*, National Chiao Tung University, *National Nano Device Laboratory

A 160-GHz receiver-based PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3rd harmonic mixer incorporating frequency tripler for frequency down conversion. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatically frequency sweeping and fast locking. The frequency locking time is less than 3 μsec. Fabricated in 65 nm CMOS technology, the chip size is 0.92mm2. This chip drains 24mW from a 1.2V power supply.

2.3 - 11:15 a.m.

A 32.4 ppm/°C 3.2-1.6V Self-chopped Relaxation Oscillator with Adaptive Supply Generation, K.-J. Hsiao, MediaTec Inc.

A self-chopped relaxation oscillator with adaptive supply generation provides the stable output clock against variations in temperature and supply voltages. The frequency drift is less than ±0.1% for the supply voltage changing from 1.6 to 3.2 V and ±0.1% for a temperature range from -20 to 100°C, which is reduced by 83% with the self-chopped technique. This relaxation oscillator is implemented in a 60-nm CMOS technology with its active area equals to 0.048 mm2. It consumes 2.8 uA from a 1.6-V supply.

2.4 - 11:40 a.m.

A 280nW, 100kHz, 1-Cycle Start-up Time, On-chip CMOS Relaxation Oscillator Employing a Feedforward Period Control Scheme, T. Tokairin, K. Nose, K. Takeda, K. Noguchi, T. Maeda, K. Kawai, M. Mizuno, Renesas Electronics Corporation

A sub-microwatt, 1-cycle start-up CMOS relaxation oscillator has been developed with a feedforward period control scheme and a digitally-controlled boost charging technique. The oscillator is implemented in 90nm CMOS and we sucessfuly have demonstrated 100kHz clock generation with ±1%-accuracy and an extremely low power consumption of 280nW.