Session 20 – TAPA I

Clock and Interconnect

Friday, June 15, 1:30 p.m.

Chairpersons: N. Kurd, Intel Corp.

R. Kuppuswamy, Intel India

20.1 - 1:30 p.m.

A Shorted Global Clock Design for Multi-GHz 3D Stacked Chips, L.-T. Pang, P. Restle, M. Wordeman, J. Silberman, R. Franch, G. Maier*, IBM TJ Watson Research Center, *IBM Systems and Technology Group

A global clock distribution technique for 3D stacked chips where the clock tree and grid are shorted between strata is presented and compared with a DLL-based technique. Both permit at-speed testing of the strata before and after stack assembly. The shorting-based technique is implemented in a 2-strata eDRAM test chip using an IBM 45nm SOI 3D technology. Operation above 2.5GHz is measured.

20.2 - 1:55 p.m.

A 3-stage Pseudo Single-phase Flip-flop Family, H. Partovi, A. Yeung, L. Ravezzi, M. Horowitz*, Veloce Technologies, Inc., *Stanford University

This paper presents an energy-efficient 3-stage Pseudo Single-phase family of Flip-flops (PSPFF) targeted for use in a 3GHz microprocessor in a 40nm, 0.9V CMOS technology. With latencies in line with the fast pulsed-latch and an average switching energy comparable to the master-slave flip-flop, PSPFF achieves an energy-delay product (EDP) which is 42% and 24% lower than the pulsed-latch and the master-slave flip-flop respectively. Measurement results confirm an improvement of at least 300MHz in operating frequency when using the PSPFF in place of the master-slave flip-flop.

20.3 - 2:20 p.m.

A Standard Cell Compatible Bidirectional Repeater with Thyristor Assist, S. Satpathy, D. Sylvester, D. Blaauw, University of Michigan

A thyristor-assisted standard cell compatible self-timed bidirectional repeater with no configuration overhead enables 8mm interconnects to achieve 37% higher speed at 20% lower energy over conventional repeaters in 65nm CMOS at 1.0V. Absence of configuration logic removes the need for clocking, yielding up to 14× higher energy efficiency at very low data switching activity.

20.4 - 2:45 p.m.

An Integral Path Self-Calibration Scheme for a 20.1-26.7GHz Dual-Loop PLL in 32nm SOI CMOS, M. Ferriss, J.-O. Plouchart, A. Natarajan, A. Rylyakov, B. Parker, A. Babakhani, S. Yaldiz, B. Sadhu, A. Valdes-Garcia, J. Tierno, D. Friedman, IBM TJ Watson Research Center

A bandwidth self-calibration scheme is introduced as part of a 20.1GHz to 26.7GHz, low noise PLL in 32nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction scheme desensitizes the loop transfer function to the VCO’s small signal gain variations. The spread of gain peaking is reduced by self-calibration from 2.4dB to 1dB, when measured at 70 sites on a 300mm wafer. The PLL has a measured phase noise @10MHz offset of -126.5dBc/Hz at 20.1GHz.