Session 22 – TAPA I

Digital Timing Generations Circuits

Friday, June 15, 3:25 p.m.

Chairpersons: A. Emami, CalTech

K. Sunaga, NEC Corp.

22.1 - 3:25 p.m.

Design of a 2.5-GHz, 3-ps Jitter, 8-Locking-Cycle, All-Digital Delay-Locked Loop with Cycle-by-Cycle Phase Adjustment, C.-Y. Cheng, J.-S. Wang, C.-T. Yeh, J.-S. Sheu, National Chung-Cheng University, *United Microelectronics Corp.

This paper describes the design of a multi-GHz ADDLL. The HDSC-based coarse-fine architecture is adopted for achieving low power and harmonic locking free when the operating frequency range is large. For preventing from long locking in GHz operations, a new resettable coarse delay line and a new asynchronous-binary-search design are proposed for achieving fast coarse and fine locking, respectively. Furthermore, a novel maintenance operation is proposed so that phase adjustment can be performed cycle by cycle to effectively suppress the jitter. Measurement results show that the designed 1.0V 55nm ADDLL has a peak-to-peak jitter of 3 ps and a locking time of 8 cycles when operated at 2.5 GHz with a power dissipation of only 1.96 mW.

22.2 - 3:50 p.m.

A 1.5GHz 1.35mW -112dBc/Hz In-band Noise Digital Phase-Locked Loop with 50fs/mV Supply-Noise Sensitivity, A. Elshazly, R. Inti, M. Talegaonkar, P.K. Hanumolu, Oregon State University

A highly digital PLL employs a 1b TDC and a low power regulator to reduce output jitter in the presence of large amount of supply-noise. Fabricated in 0.13μm CMOS, the ring-oscillator based DPLL consumes 1.35mW at 1.5GHz output frequency and achieves better than 50fs/mV worst-case noise sensitivity (º10pspp jitter degradation with 200mVpp noise). The proposed DPLL achieves the lowest power, and the best reported supply noise rejection compared to state-of-the-art PLLs.

22.3 - 4:15 p.m.

A 61-dB SNDR 700 µm² Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops, T. Konishi, K. Okuno, S. Izumi, M. Yoshimoto, H. Kawaguchi, Kobe University

We present a small-area second-order all-digital time-to-digital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter chains and dynamic flipflops featuring low jitter. The proposed FSOs can maintain their phase states through continuous oscillation, unlike conventional gated ring oscillators (GROs) that are affected by transistor leakage. Our proposed FSOTDC is more robust and is eligible for all-digital TDC architectures in recent leaky processes. Low-jitter dynamic flipflops are adopted as a quantization noise propagator (QNP). A frequency mismatch occurring between the two FSOs can be canceled out using a least mean squares (LMS) filter so that second-order noise shaping is possible. In a standard 65-nm CMOS process, an SNDR of 61 dB is achievable at an input bandwidth of 500 kHz and a sampling rate of 16 MHz, where the respective area and power are 700 µm2 and 281 μW.

22.4 - 4:40 p.m.

A 7b, 3.75ps Resolution Two-Step Time-to-Digital Converter in 65nm CMOS Using Pulse-Train Time Amplifier, K. Kim, Y. Kim, W. Yu, S. Cho, KAIST

This paper presents a time-to-digital converter (TDC) using a novel pulse-train time amplifier. The proposed TDC exploits repetitive pulses with gated delay-lines for a calibration-free and programmable time amplification and quantization. Using this circuit, a 7-bit two-step time-to-digital converter is implemented. The prototype chip fabricated in 65nm CMOS process achieves 3.75ps of time resolution at 200Msps while consuming 3.6mW and occupying 0.02mm2.