Session 4 – TAPA I

A/D Converters

Wednesday, June 13, 1:30 p.m.

Chairpersons: T.C. Carusone, University of Toronto

M. Ito, Renesas Electronics Corp.

4.1 - 1:30 p.m.

A 6b 3GS/s 11mW Fully Dynamic Flash ADC in 40nm CMOS with Reduced Number of Comparators, Y.-S. Shu, MediaTek Inc.

A 6b 3GS/s fully dynamic flash ADC is fabricated in 40nm CMOS and occupies 0.021mm2. Dynamic comparators with digitally controlled built-in offset are realized with imbalanced tails. Half of the comparators are substituted with simple SR latches. The ADC achieves SNDRs of 36.2dB and 33.1dB at DC and Nyquist, respectively, while consuming 11mW from a 1.1V supply.

4.2 - 1:55 p.m.

An Event-Driven, Alias-Free ADC with Signal-Dependent Resolution, C. Weltin-Wu, Y. Tsividis, Columbia University

A clockless 8b ADC in 130nm CMOS uses a time-varying comparison window to dynamically vary resolution, and input-dependent dynamic bias, to maintain SNDR while saving power. Alias-free operation with SNDR in the range of 47-54dB, which partly exceeds the theoretical limit of 8b conventional converters, is achieved over a 20kHz bandwidth with 3-9µW power from a 0.8V supply.

4.3 - 2:20 p.m.

A 10-Bit 1-GHz 33-mW CMOS ADC, B.D. Sahoo, B. Razavi, University of California, Los Angeles

A pipelined ADC digitally calibrates capacitor mismatches in its 4-bit first stage and the gain error in the first 5 stages. Using a one-stage op amp with a gain of 10 and realized in 65-nm CMOS technology, the ADC digitizes a 490-MHz input with an SNDR of 52.4 dB, achieving an FOM of 0.097pJ/conversion-step.

4.4 - 2:45 p.m.

A 61.5dB SNDR Pipelined ADC Using Simple Highly-Scalable Ring Amplifiers, B. Hershberg, S. Weaver, K. Sobue*, S. Takeuchi*, K. Hamashita*, U.-K. Moon, Oregon State University, Asahi Kasei Microdevices

A ring amplifier based pipelined ADC is presented that uses simple cells constructed from small inverters and capacitors to perform amplification. The basic ring amplifier structure is characterized and demonstrated to be highly scalable, power efficient, and compression-immune (inherent rail-to-rail output swing). The prototype 10.5-bit ADC, fabricated in 0.18µm CMOS technology, achieves 61.5dB SNDR at a 30MHz sampling rate and consumes 2.6mW, resulting in

a FoM of 90fJ/conversion-step.