CIRCUITS SESSION 6 – TAPA I

Technology/Circuits Joint Focus Session - Emerging Nonvolatile Memory

Wednesday, June 13, 3:25 p.m.

Chairpersons: J. DeBrosse, IBM

S. Yamakawa,Sony Corp.

6.1 - 3:25 p.m.

A 0.13μm 8Mb Logic Based Cu_xSi_yO Resistive Memory with Self-Adaptive Yield Enhancement and Operation Power Reduction, X.Y. Xue, W.X. Jian, J.G. Yang, F.J. Xiao, G. Chen, X.L. Xu, Y.F. Xie, Y.Y. Lin, R. Huang*, Q.T. Zhou*, J.G. Wu*, Fudan University, *Semiconductor Manufactoring International Corp.

A 0.13μm 8Mb CuxSiyO resistive memory test macro with 20F2 cell size is developed based on logic process for the first time. Smart and adaptive assist write and read circuit are proposed and verified in order to fix yield and power consumption issues from large write speed and high temperature resistance variation. SAWM (self-adaptive write mode) helps to enlarge Roff/Ron window from 8X to 24X at room temperature. The reset bit yield is improved from 61.5% to 100% and large power consumption is eliminated after set success. SARM (Self-adaptive read mode) improves read bit yield from 98% to 100% at 125℃.

The typical access time of on-pitch voltage sensing SA(sense amplifier) is 21ns and high bandwidth throughput is supported.

6.2 - 3:50 p.m.

A 3.14 um² 4T-2MTJ-Cell Fully Parallel TCAM Based on Nonvolatile Logic-in-Memory Architecture, S. Matsunaga, S. Miura*, H. Honjou*, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu, Tohoku University, *NEC Corporation

A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free and a high-density fully parallel nonvolatile TCAM. By optimally merging a nonvolatile storage function and a comparison logic function into a TCAM cell circuit with a nonvolatile logic-in-memory structure, the transistor counts required in the cell circuit become minimized. As a result, the cell size becomes 3.14um2 under a 90-nm CMOS and a 100-nm MTJ technologies, which achieves 60% and 86% of area reduction in comparison with that of a 12T-SRAM-based and a 16T-SRAM-based TCAM cell circuit, respectively.

6.3 - 4:15 p.m.

1Mb 4T-2MTJ Nonvolatile STT-RAM for Embedded Memories Using 32b Fine-Grained Power Gating Technique with 1.0ns/200ps Wake-up/Power-off Times, T. Ohsawa, H. Koike, S. Miura*, H. Honjo*, K. Tokutome*, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh, Tohoku University, *NEC Coropration

A 1Mb nonvolatile STT-RAM using the 4T-2MTJ cell is designed and fabricated using 90nm CMOS and MTJ processes. 32 cells along a word line (WL) are simultaneously power-gated with quick wake-up/power-off times of 1.0ns/200ps, respectively, to reduce operation power and to eliminate standby power of the chip. The cell is experimentally shown to retain data with static noise margin (SNM) 0.32V under Vdd=1V. The 1Mb chip with 2.19um2 cell is successfully operated with array access time of 8ns and read power of 10.7mW under 10ns cycle. The macro size of 1Mb STT-RAM is predicted to become smaller than the 1Mb 6T-SRAM in 45nm and beyond.

T-6.4 - 4:40 p.m.

A Simple New Write Scheme for Low Latency Operation of Phase Change Memory, Y.-Y. Lin, Y.-C. Chen, F.-M. Lee, M. BrightSky*, H.-L. Lung, C. Lam*, Macronix International Co., Ltd., *IBM T.J. Watson Research Center

The behavior of resistance drift after RESET operation for phase change memory is investigated. We propose, for the first time, an effective way to accelerate the drift so that the program/read latency may better match that for DRAM for SCM (storage class memory) application. By simply applying an extra annealing pulse after RESET we can quickly anneal out many defects (that are responsible for the drift) and provide a drift-free period that enlarges the read window. A physical model is proposed to understand the defect annealing phenomenon, which predicts the resistance drift behavior well.

T-6.5 - 5:05 p.m.

Analysis of Random Telegraph Noise and Low Frequency Noise Properties in 3-D Stacked NAND Flash Memory with Tube-Type Poly-Si Channel Structure, M.-K. Jeong, S.-M. Joe, C.-S. Seo, K.-R. Han*, E. Choi*, S.-K. Park*, J.-H. Lee, Seoul National University, *Hynix Semiconductor Inc.

Random Telegraph Noise (RTN) and low frequency noise (LFN) properties were investigated for the first time in 3-D stacked NAND flash memory with tube-type poly-Si channel structure. 3-D stacked NAND flash memory showed higher noise power density of bit-line (BL) current (IBL) by ~10 times than 32 nm NAND flash memory. The behavior of DIBL was investigated with control-gate bias (VCG), BL bias (VBL) and pass bias (Vpass). As temperature (T) increases, capture and emission times becomes short. To understand poly-Si channel, planar poly-Si thin film transistors (TFT) with different grain size were prepared and analyzed in terms of noise, subthreshold swing (SS), and T.