CIRCUITS SESSION 8 – TAPA I

Technology/Circuit Joint Focus Session - Advanced SRAM

Thursday, June 14, 8:05 a.m.

Chairpersons: G. Lehmann, Infineon Technologies AG

H. Yamauchi, Fukuoka Institute of Technology

8.1 - 8:05 a.m.

A 0.41μA Standby Leakage 32Kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28nm HKMG CMOS, N. Maeda, S. Komatsu, M. Morimoto, Y. Shimazaki, Renesas Electronics Corp.

A high-performance and low-leakage current embedded SRAM for mobile phones is proposed. The proposed SRAM has a low-voltage resume-standby mode to reduce the standby leakage. An all digital current comparator is also proposed to choose a suitable standby mode. A test chip was fabricated using 28 nm HKMG CMOS technology. The proposed 32 Kb SRAM has a 0.41 μA standby leakage which is the conventional half, with 420 ps access.

8.2 - 8:30 a.m.

A 13.8pJ/Access/Mbit SRAM with Charge Collector Circuits for Effective Use of Non-Selected Bit Line Charges, S. Moriwaki, Y. Yamamoto, A. Kawasumi, T. Suzuki*, S. Miyano, T. Sakurai**, H. Shinohara, Semiconductor Technology Academic Research Center, *Panasonic Corp., **University of Tokyo

1Mb SRAM with charge collector circuits for effective use of non-selected bit line charges has been fabricated in 40nm technology. These circuits reduce two major wasted power sources of the low voltage SRAM: excess bit line swing due to random variation and bit line swing of non-selected columns. The lowest power consumption of 13.8pJ/Access/Mbit in the previous works has been achieved.

8.3 - 8:55 a.m.

A SRAM Cell Array with Adaptive Leakage Reduction Scheme for Data Retention in 28nm High-K Metal-Gate CMOS, P. Hsu, Y. Tang, D. Tao, M.-C. Huang, M.-J. Wang, C. Wu, Q. Li, TSMC

1Mbit SRAM macro with adaptive leakage current reduction scheme is implemented in 28nm high-k metal gate CMOS technology. A current limiter that limits cell array leakage current at various process-voltage-temperature (PVT) corners is included in the proposed scheme. The leakage current is reduced by more than 60% at fast process corners by increasing virtual ground voltage (Vvgnd) while maintaining sufficient data retention margin. At low VDD or slow process corners, Vvgnd is lowered to maintain the data integrity in the bitcell.

8.4 - 9:20 a.m.

A 28nm High-k Metal-Gate SRAM with Asynchronous Cross-Couple Read Assist (AC2RA) Circuitry Achieving 3X Reduction on Speed Variation for Single Ended Arrays, R. Lee, J.-P. Yang, C.-E. Huang, C.-C. Chiu, W.-S. Kao, H.-C. Cheng, H.-J. Liao, J. Chang, TSMC

Asynchronous Cross-Couple Read Assist (AC2RA) circuitry scheme was invented for single-ended sensing to minimize speed variation in 28nm HKMG process. It improves SRAM array speed variation by 63.3% which is adequate to cover 6s variation. Access time is also boosted by faster sensing.