2012 VLSI Circuits Short Course Program

Honolulu I

Designing in Advanced Cmos Technologies

Tuesday, June 12

8:30 am. – 5:30 p.m.

Organizers/Chairs: Andreia Cathelin, STMicroelectronics

Masato Motomura, Hokkaido University

8:30 a.m. Introduction

Andreia Cathelin, STMicroelectronics

8:45 a.m. Bulk CMOS Scaling to the End of the Roadmap

Tsu-Jae King Liu, UC Berkeley

9:45 a.m. Technology Boosters for LP Design Platforms in 28/20nm

Thomas Skotnicki, STMicroelectronics

10:45 a.m. Break

11:00 a.m. Challenges and Solutions Paths in Scaling SRAM

Fatih Hamzaoglu, Intel

12:00 p.m. Lunch

1:00 p.m . The Mixed-Signal Design Challenges in the Advanced Technology Nodes

Fu-Lung Hsueh, TSMC

2:00 p.m. Power-aware Design in 28nm Generation and Beyond-Facts, Myths, and Misunderstandings

Youngsoo Shin, Kaist

3:00 p.m. Break

3:15 p.m. Advanced CAD Methodologies for Custom Design at Advanced Process Nodes

David White, Cadence R&D

4:15 p.m. Round Table Discussion

All Speakers