Technology Session 10 – TAPA 3

Technology / Circuits Joint Focus Session – Memory

Wednesday, June 13, 10:25 a.m.

Chairs: J. Zahurak, Micron Technology

M. Hane, Renesas Electronics Corp.

10.1 – 10:25 a.m.

SRAMs using Tri-Gate Transistors, K. Zhang, Intel Corp.

10.2 – 10:50 a.m.

Hybrid Memory Cube New DRAM Architecture Increases Density and Performance, J. Jeddeloh, B. Keeth, Micron

10.3 – 11:15 a.m.

STT Technology and Design Co-Optimization, T. Endoh, Center for Spintronics Integrated Systems

10-4 - 11:40 a.m.

A Highly Pitch Scalable 3D Vertical Gate (VG) NAND Flash Decoded by a Novel Self-Aligned Independently Controlled Double Gate (IDG) String Select Transistor (SSL), C.-P. Chen, H.-T. Lue, K.-P. Chang, Y.-H. Hsiao, C.-C. Hsieh, S.-H. Chen, Y.-H. Shih, K.-Y. Hsieh, T. Yang, K.-C. Chen, C.-Y. Lu, Macronix International., Ltd.

Despite vertical stacking, the lateral scaling of 3D NAND Flash is critically important because otherwise >16 stacking layers are needed to be cost competitive to 20nm 2D NAND. In this work, we propose a 3D vertical gate (VG) NAND using a self-aligned independently controlled double gate (IDG) string select transistor (SSL) decoding method. The IDG SSL provides excellent program inhibit and read selection without any penalty of cell size increase, making our 3D VG NAND cell as scalable as conventional 2D NAND. We present the world’s first < 50nm (37.5nm) half-pitch 3D NAND. The BL decoding and page operation methods are illustrated in detail. This highly pitch scalable VG with IDG SSL approach provides a very cost competitive 3D NAND.