Technology Session 12 – TAPA 3

Technology / Circuits Joint Focus Session – 3D-System Integration

Wednesday, June 13, 1:30 p.m.

Chairs: A. Antonelli,Novellus Systems, Inc.

T. Tanaka, Tohoku Univ.

12.1 – 1:30 p.m.

Practical Implications of Via-Middle Cu TSV-induced Stress in a 28nm CMOS Technology for Wide-IO Logic-Memory Interconnect, J. West, Texas Instruments

12.2 – 1:55 p.m.

Thermal Stress Characteristics and Impact on Device Keep-Out Zone for 3-D ICs Containing Through-Silicon-Vias – T. Jiang, S-K Ryu, Q. Zhao, J. Im, H-Y Son, K-Y Byun, R. Huang, P.S. Ho, University of Texas, Austin and Hynix

12.3 – 2:20 p.m.

Near-Field Wireless Connection for 3D-system Integration, T. Kuroda, Keio University

12-4 - 2:45 p.m.

An Ultra-Thin Interposer Utilizing 3D TSV Technology, W.-C. Chiou, K.-F. Yang, C. Yeh, S.-H. Wang, Y.-H. Liou, T.-J. Wu, J.-C. Lin, C.-C. Hsieh, H.A. Teng, C.C. Chiu, D.C. Yeh, W.C. Wu, A.J. Su, S.L. Chiu, H.-P. Chang, J. Wei, Y.-C. Lin, Y.-H. Chen, H.-J. Tu, H.D. Ko, T.-H. Yu, J.P. Hung, P.-H. Tsai, C.L. Huang, S.W. Lu, S.Y. Hou, D.-Y. Shih, K.H. Chen, S.-P. Jeng, C.-H. Yu, TSMC

To achieve ultra small form factor package solution, an ultra-thin (50μm) Si interposer utilizing through-silicon-via (TSV) technology has been developed. Challenges associated with handling thin wafer and maintaining package co-planarity have been overcome to stack thin dies (200μm) on ultra-thin interposer. Improved electrical performance and the advantages of this innovative thin interposer are highlighted in this paper. Warpage behavior is investigated with simulation and experiments to ensure reliability and robustness of the Si stack. Reduction in package thickness is realized to achieve high functionality, small form factor, better electrical performance and robust reliability by stacking thin dies on ultra-thin interposer.