Technology Session 17 – TAPA 2

Technology / Circuits Joint Focus Session – Design in Scaled Technologies

Thursday, June 14, 10:00 a.m.

Chairs: J. Cheek, Freescale

R. Takemura, Hitachi, Ltd.

17.1 – 10:00 a.m.

Design Enablement at 14nm: The Challenge of Being Early, Accurate, and Complete, L. Salmon, Texas Instruments

17.2 – 10:25 a.m.

Designing in Scaled Technologies: 32nm and Beyond, S. Kosonocky, AMD

17.3 – 10:50 a.m.

RFCMOS in Scaled Technologies, T. Ohguro, Toshiba

C-17.4 – 11:15 a.m.

Dynamic Intrinsic Chip ID Using 32nm High-K/Metal Gate SOI Embedded DRAM, D. Fainstein, S. Rosenblatt, A. Cestero, N. Robson, T. Kirihata, S.S. Iyer, IBM Systems and Technology Group

A random intrinsic chip ID method generates a pair of 4Kb binary strings using retention fails in 32nm SOI embedded DRAM. Hardware results show ID overlap distance mean=0.58 and σ=0.76 and demonstrate 100% authentication for 346 chips. The analytical model predicts > 99.999% unique IDs for 10^6 parts.

C-17.5 – 11:40 a.m.

A Fully-Digital Phase-Locked Low Dropout Regulator in 32nm CMOS, A. Raychowdhury, D. Somasekhar, J. Tschanze, V. De, Intel Corp.

A fully-digital phase-locked low dropout regulator (LDO) has been designed in 32nm CMOS for fine-grained power delivery to multi-Vcc digital circuits. Measurements across a wide range of input voltages and currents exhibit that the LDO offers excellent load regulation and efficiency close to 97% of ideal efficiency at nominal load current conditions (ILOAD=3mA).