Technology Rump Sessions

Tuesday, June 12, 8:00 p.m. – 10:00 p.m.

JOINT TECHNOLOGY/CIRCUITS RUMP SESSION

Tuesday, June 12

8:00 p.m. – 10:00 p.m.

Organizers:

Circuits

N. Lu, Etron

M. Bauer, Micron

Technology

T. Skotnicki, STMicroelectronics

K. Miyashita, Toshiba

RJ1: Scaling Challenges Beyond 1x nm DRAM and NAND Flash

Moderator: R. Shrivastava, SanDisk

N. Lu, Etron

The combined revenues of DRAM and NAND Flash approached $54 Billion in 2010. This is expected to continue to grow in the coming years. Emerging silicon and package technologies will further drive lower cost and new applications. The difficulty of scaling and developing new technologies and investments to build new factories is increasing at about the same rate as the memory bit growth in the world. At the same time, the industry is becoming aware that we are closing in on physical and electrical scaling limitations. As we close in on scaling limits, the use of new materials, manufacturing processes, and circuit design will become unavoidable. To compound the problem, fierce competition is forcing shorter development times. Our industry needs to openly address these issues and challenges in order to continue developing better and lower cost memories for the decade to come. The whole industry faces these challenges and issues. They are huge. We have assembled a representative group of industry experts for this Joint Rump Session. We will ask them to discuss the top issues from the perspective of each one’s area of expertise. The floor will be open to question the panelist's view or challenge them to consider issues that audience would like to raise.

Panelists:

S. Aritome, Hynix

G. Atwood, Micron

G. Bronner, Rambus

H. Hazama, Toshiba

H-K Kang, Samsung

C.Y. Lu, Macronix

M. Koyanagi, Tohoku University

K. Takeuchi, University of Tokyo

R2: Evolution of FinFET and beyond?

Moderators: G. Yeap, Qualcomm

Y. Miyamoto, Tokyo Institute of Technology

As conventional scaling approaches its limits, the semiconductor industry has been evaluating for more than a decade on 3D multi-gate FINFET/Tri-gate transistors as well as planar transistors with alternative channel designs (such as FD-SOI, Ge, III-V) for achieving the power efficiency, performance, density, reliability, and form factor required in advanced mobile devices.

It is extremely exciting that in 2012 the industry finally enters into the 3-D era with the high volume production of 3-D Tri-gate/FinFET transistors in 22nm standalone CPU technology. Did 1^st generation 3-D tri-gate transistor fully deliver the power/performance value proposition, and achieve the required density/cost and reliability? How well can multi-gate 3D or alternative channel designs overcome scaling bottlenecks, such as parasitic R&C and variability? How fast the 3-D transistor production will spread to other applications especially the driver application of mobile computing SoC? Will 3-D transistor technology completely and utterly dominate the industry or there are rooms for planar architecture be extended or enhanced for a cost/PPA sweatspot for certain applications/markets? How will the 2^nd/3^rd generation 3-D technology look like? How best the 3-D transistor technology coupled with 2.5/3-D interconnect technology to deliver holistic system scaling for complex, power constrained mobile computing and wireless applications? What is life after FinFET – any Joker left in the pocket?

This panel moderated by Geoffrey Yeap/Y. Miyamoto will start out with a "fire side chat" on the issues from each panelist's perspective, and evolve into a what we hope is a passionate discussion with some serious audience participation. The panelists whose views range across the spectrum include:

Panelists

F. Boeuf, STMicroelectronics

J.P. Colinge, TSMC

W. Haensch, IBM

D.W. Kim, Samsung

A. Thean, imec

S. Thompson, SuVolta

R3: Advanced Patterning for Next Generation Technology Nodes: EUV or Tricky-193nm, EBDW? DSA, Resists, Masks, Regular Layouts, Metrology?

Moderators : G. Vandenberghe, IMEC

M. Tomoyasu, Tokyo Electron

To EUV or not to EUV? That is at least one of the questions that will be tackled by all panelists. In this rump session, the lithography/patterning challenges to enable further scaling will be discussed by multiple experts, involved in the many different fields of lithography as chipmaker, fabless company or equipment manufacturer. What are the ultimate limits of 193nm immersion lithography with multiple patterning schemes? What is the manufacturability readiness of EUV lithography? And how about ebeam direct write? Can directed self assembly be seen as an extension technique? Are only unidirectional layouts allowed and how will the EDA tackle the patterning complexity? What will be the patterning demand from under layer materials and structure direction? How will the metrology enable the lithography challenges?

Y. Borodovsky, Intel

A. Chen, ASML

H. Levinson, GlobalFoundries

B. Lin, TSMC

S. Nagahara, TEL

A. Yamaguchi, Hitachi