Session 10 – TAPA 3

Technology / Circuits Joint Focus Session – Memory

Wednesday, June 13, 10:25 a.m.

Chairs: J. Zahurak, Micron Technology

M. Hane, Renesas Electronics Corp.

10.1 – 10:25 a.m.

SRAMs Design in Nano-Scale CMOS Technologies (Invited), K. Zhang, Intel Corp.

SRAM continues to serve as the workhorse of embedded memory for all modern VLSI systems. But SRAM scaling has become increasingly challenging in meeting both power and density requirements due to relentless miniaturization in the 6T SRAM cell area. Innovative circuit technologies along with key process advancement are discussed and they have been proven to be essential for the SRAM scaling to continue to follow Moore’s law well into the future.

10.2 – 10:50 a.m.

Hybrid Memory Cube New DRAM Architecture Increases Density and Performance (Invited),

J. Jeddeloh, B. Keeth, Micron

Multi-core processor performance is limited by memory system bandwidth. The Hybrid Memory Cube is a three-dimensional DRAM architecture that improves latency, bandwidth, power and density.   Through-silicon vias (TSVs), 3D packaging and advanced CMOS performance enable a new approach to memory system architecture.   This talk will cover the architecture, design methodology, TSV process challenges and trade-offs of Micron’s Hybrid Memory Cube.

10.3 – 11:15 a.m.

Restructuring of Memory Hierarchy in Computing System with Spintronics-Based Technologies (Invited), T. Endoh, T. Ohsawa, H. Koike, T. Hanyu, H. Ohno, Tohoku University

The restructuring of memory hierarchies that are caught in a dilemma between performance-gain and power-reduction is one of the most promising ways to achieving the high-end and low-power computers. To this end, several possibilities of using NV memories and NV logic with STT-MTJ as levels in new hierarchies are discussed. A new NV-SRAM cell consisting of four transistors and two MTJs is shown to be a promising candidate for NV-cache memories. For NV-main memories, we propose a PFET-based 1T-1MTJ cell. A new NV-latch that can be constructed in flip-flops of synchronous circuits is proposed and 600MHz operation is experimentally demonstrated.

10.4 - 11:40 a.m.

A Highly Pitch Scalable 3D Vertical Gate (VG) NAND Flash Decoded by a Novel Self-Aligned Independently Controlled Double Gate (IDG) String Select Transistor (SSL), C.-P. Chen, H.-T. Lue, K.-P. Chang, Y.-H. Hsiao, C.-C. Hsieh, S.-H. Chen, Y.-H. Shih, K.-Y. Hsieh, T. Yang, K.-C. Chen, C.-Y. Lu, Macronix International., Ltd.

Despite vertical stacking, the lateral scaling of 3D NAND Flash is critically important because otherwise >16 stacking layers are needed to be cost competitive to 20nm 2D NAND. In this work, we propose a 3D vertical gate (VG) NAND using a self-aligned independently controlled double gate (IDG) string select transistor (SSL) decoding method. The IDG SSL provides excellent program inhibit and read selection without any penalty of cell size increase, making our 3D VG NAND cell as scalable as conventional 2D NAND. We present the world’s first < 50nm (37.5nm) half-pitch 3D NAND. The BL decoding and page operation methods are illustrated in detail. This highly pitch scalable VG with IDG SSL approach provides a very cost competitive 3D NAND.