Session 11 – TAPA 2

Mobility Enhancement

Wednesday, June 13, 1:30 p.m.

Chairs: M. Mehrotra, Texas Instruments

S. Takagi, The University of Tokyo

11.1 - 1:30pm

A New Liner Stressor (GeTe) Featuring Stress Enhancement due to Very Large Phase-Change Induced Volume Contraction for p-Channel FinFETs, R. Cheng, Y. Ding, S.M. Koh, A. Gyanathan, F. Bai, B. Liu, Y.-C. Yeo, National University of Singapore

We report the first demonstration of a novel GeTe liner stressor which exhibits very large volume contraction during phase-change, and its integration in p-channel FinFETs for strain engineering. Conformally grown GeTe liner with different thicknesses was formed on FinFETs with ultra-scaled gate length LG down to ~3 nm. When GeTe changes phase from amorphous (α-GeTe) to crystalline state (c-GeTe), GeTe liner contracts and compresses the Si source/drain region in the fin, leading to very high channel stress. Significant drive current IDsat enhancement of 69% and 106% were observed for FinFETs with 30 nm and 50 nm c-GeTe liner stressor over the control devices, respectively.

11.2 - 1:55pm

GeSn Channel nMOSFETs: Material Potential and Technological Outlook, S. Gupta, B. Vincent*, D. Lin*, M. Gunji, A. Firrincieli*, F. Gencarelli*, B. Magyari-Köpe, B. Yang**, B. Douhard*, J. Delmotte*, A. Franquet*, M. Caymax*, J. Dekoster*, Y. Nishi, K. Saraswat, Stanford University, *IMEC, **GLOBALFOUNDRIES

Semiconducting germanium tin (GeSn) alloy has recently emerged as a candidate for high performance CMOS and optoelectronic devices because of its tunable direct gap and potential for high electron and hole mobilities. High hole mobility in GeSn channel pMOSFETs has already been demonstrated. However, GeSn as channel for nMOSFETs has not yet been explored. In this work we perform detailed theoretical analysis to gauge the benefits of GeSn channel over Ge for nMOSFETs. Our analysis predicts GeSn nMOSFETs to outperform Ge. GeSn n-channel devices have been successfully fabricated and factors limiting its performance are investigated, potential solutions are presented.

11.3 - 2:20pm

Strained Germanium-Tin (GeSn) N-Channel MOSFETs Featuring Low Temperature N⁺/P Junction Formation and GeSnO₂ Interfacial Layer, G. Han, S. Su*, L. Wang, W. Wang, X. Gong, Y. Yang, Ivana, P. Guo, C. Guo, G. Zhang*, J. Pan**, Z. Zhang**, C. Xue*, B. Cheng*, Y.-C. Yeo, National University of Singapore, *Chinese Academy of Sciences, **A*STAR

In this paper, we report the world’s first germanium-tin (GeSn) channel nMOSFETs. Highlights of process module advances are: low temperature (400 ˚C) process for forming high quality n+/p junction with high dopant activation and reduced dopant diffusion; interface engineering achieved with GeSnO2 interfacial layer (IL) between high-k gate dielectric and GeSn channel. A gate-last process was employed. The GeSn nMOSFET with GeSnO2 IL demonstrates a substantially improved SS in comparison with Ge control, and an ION/IOFF ratio of 104.

11.4 - 2:45pm

Towards High Performance Ge_1-xSn_x and In_0.7Ga_0.3As CMOS: A Novel Common Gate Stack Featuring Sub-400 ºC Si₂H₆ Passivation, Single TaN Metal Gate, and Sub-1.3 nm EOT, X. Gong, S. Su*, B. Liu, L. Wang, W. Wang, Y. Yang, E. Kong, B. Cheng*, G. Han, Y.C. Yeo, National University of Singapore, *Chinese Academy of Sciences

We report a novel common gate stack solution for Ge1-xSnx P-MOSFET and In0.7Ga0.3As N-MOSFET, featuring sub-400 ºC Si2H6 passivation, sub-1.3 nm EOT, and single TaN metal gate. Symmetric VTH, high performance, low gate leakage, negligible hysteresis, and excellent reliability were realized. Using this gate stack, the world’s first GeSn short-channel device with gate length LG down to 250 nm was realized. Drive current of more than 1000 µA/µm was achieved, with peak intrinsic transconductance of ~ 465 μS/μm at VDS of -1.1 V.