Session 12 – TAPA 3

Technology / Circuits Joint Focus Session – 3D-System Integration

Wednesday, June 13, 1:30 p.m.

Chairs: A. Antonelli,Novellus Systems, Inc.

T. Tanaka, Tohoku Univ.

12.1 – 1:30 p.m.

Practical Implications of Via-Middle Cu TSV-induced Stress in a 28nm CMOS Technology for Wide-IO Logic-Memory Interconnect (Invited), J. West, Y.S. Choio, C. Vartuli, Texas Instruments

The impact of isolated and arrayed 10x60mm via-middle Cu TSVs on 8LM 28nm node CMOS poly-SiON P/NFETs was electrically measured for proximities >4 mm at 27C and 105C. The largest observed shift in I_on (<2.3%) is significantly less than that from other context-dependent sources such as dual stress liner boundaries (~10%). NanoBeam Diffraction measurements of Si strain within 5mm of TSVs were acquired for samples prepared from fully processed wafers, showing that for proximity >1.5mm the impact of TSVs is negligible. Interaction with overlying interconnect is mitigated through optimization of post-TSV plating anneal to achieve <200Å Cu pumping and by introducing a TSV unit cell designed to minimize the impact on local environment.

12.2 – 1:55 p.m.

Thermal Stress Characteristics and Impact on Device Keep-Out Zone for 3-D ICs Containing Through-Silicon-Vias (Invited),T. Jiang, S-K Ryu, Q. Zhao, J. Im, H-Y Son, K-Y Byun, R. Huang, P.S. Ho, University of Texas, Austin and Hynix

Thermal stresses in TSV structures have been measured using micro-Raman spectroscopy and precision wafer curvature technique as a function of temperature and during thermal cycling. The results were verified by finite element analysis (FEA) to characterize the thermal stress behavior of the TSV structures. A nonlinear stress relaxation was observed during initial heating and no preferred grain orientation was found, indicating a homogeneous Cu grain structure with no pronounced elastic anisotropy. The stress impact on the keep-out zone (KOZ) for devices near the TSVs was investigated.

12.3 – 2:20 p.m.

Near-Field Wireless Connection for 3D-System Integration (Invited), T. Kuroda, Keio University

This paper describes a near-field wireless connection using inductive coupling, namely ThruChip Interface (TCI). TCI is a digital CMOS circuit solution in a standard CMOS technology. It is much less expensive than TSV but bears comparison in performance. Aggregated data rate of 8Tb/s is achieved by arranging 1000 channels in 6.4 mm². Energy consumption is 0.01pJ/b. Delay and energy dissipation will scale down by device miniaturization. If chip thickness is also thinned to 1/α, both electric field of FET and magnetic field of TCI are kept constant and aggregated data rate per area is increased by α³ and energy per bit is reduced to 1/α³.

12-4 - 2:45 p.m.

An Ultra-Thin Interposer Utilizing 3D TSV Technology, W.-C. Chiou, K.-F. Yang, C. Yeh, S.-H. Wang, Y.-H. Liou, T.-J. Wu, J.-C. Lin, C.-C. Hsieh, H.A. Teng, C.C. Chiu, D.C. Yeh, W.C. Wu, A.J. Su, S.L. Chiu, H.-P. Chang, J. Wei, Y.-C. Lin, Y.-H. Chen, H.-J. Tu, H.D. Ko, T.-H. Yu, J.P. Hung, P.-H. Tsai, C.L. Huang, S.W. Lu, S.Y. Hou, D.-Y. Shih, K.H. Chen, S.-P. Jeng, C.-H. Yu, TSMC

To achieve ultra small form factor package solution, an ultra-thin (50μm) Si interposer utilizing through-silicon-via (TSV) technology has been developed. Challenges associated with handling thin wafer and maintaining package co-planarity have been overcome to stack thin dies (200μm) on ultra-thin interposer. Improved electrical performance and the advantages of this innovative thin interposer are highlighted in this paper. Warpage behavior is investigated with simulation and experiments to ensure reliability and robustness of the Si stack. Reduction in package thickness is realized to achieve high functionality, small form factor, better electrical performance and robust reliability by stacking thin dies on ultra-thin interposer.