Session 13 – TAPA 2

Ultra-Thin Body Devices

Wednesday, June 13, 3:25 p.m.

Chairs: M. Khare, IBM

C.H. Wann, TSMC

13.1 - 3:25 p.m.

Poly/High-k/SiON Gate Stack and Novel Profile Engineering Dedicated for Ultralow-Voltage Silicon-on-Thin-BOX (SOTB) CMOS Operation, Y. Yamamoto, H. Makiyama, T.Tsunomura, T. Iwamatsu, H. Oda, N. Sugii, Y. Yamaguchi, T. Mizutani*, T. Hiramoto, LEAP, *University of Tokyo

We demonstrated Silicon on Thin Buried oxide (SOTB) CMOS especially designed for ultralow-voltage (ULV) operation down to 0.4 V for the first time. Utilizing i) dual-poly gate stack with high-k having quarter-gap work functions best for the ULV CMOS operation, and ii) a novel “local ground plane (LGP)” structure that significantly improves short-channel effect (Vth roll off) without increasing local variability unlike halo for bulk, low-leakage SRAM operation was demonstrated with adaptive-body-bias (ABB) scheme.

13.2 - 3:50 p.m.

Efficiency of Mechanical Stressors in Planar FDSOI n and p MOSFETs Down to 14nm Gate Length, S. Morvan, F. Andrieu, M. Cassé, O. Weber, N. Xu, P. Perreau, J.-M. Hartmann, J.-C. Barbé, J. Mazurier, P. Nguyen*, C. Fenouillet-Bérangee, C. Tabone, L. Tosti, L. Brévard, A. Toffoli, F. Allain, D. Lafond, B.-Y. Nguyen*, G. Ghibaudo^, F. Boeuf**, O. Faynot, T. Poiroux, CEA, LETI, MINATEC, *SOITEC, **STMicroelectronics, ^IMEP-LAHC/MINATEC

We fabricated highly stressed Fully Depleted Silicon-On-Insulator (FDSOI) n and pMOSFETs reaching ION,n/ION,p=1148/1014µA/µm drive current at IOFF,n/IOFF,p=55/16nA/µm leakage current (VDD=1V) with excellent VT-matching (AVT<1.5mV.µm). These short channel performances are well correlated and quantitatively explained by the effectiveness of strained SOI (sSOI), Contact-Etch-Stop-Layers (CESL) and SiGe raised sources and drains. sSOI improves ION,n up to 22% and degrades SiGe sources and drains efficiency for pMOSFETs. However, 0° (<110>) orientation remains the best configuration for high-stress pMOSFETs and provides the best trade-off for CMOS.

13.3 - 4:15 p.m.

Impact of Back Biasing on Carrier Transport in Ultra-Thin-Body and BOX (UTBB) Fully Depleted SOI MOSFETs, N. Xu, F. Andrieu*, B. Ho, B.-Y. Nguyen*, O. Weber*, C. Mazure*, O. Faynot*, T. Poiroux*, T.-J. King Liu, University of California, Berkeley, *CEA-LETI, Minatec, **SOITEC

A comprehensive study of the impact of back biasing on carrier transport behavior in Ultra-Thin Body and BOX (UTBB) Fully Depleted SOI (FD-SOI) MOSFETs and its implications for deeply scaled device performance is presented.

13.4 - 4:40 p.m.

Enhancement of Devices Performance of hybrid FDSOI/Bulk Technology by using UTBOX sSOI substrates, C. Fenouillet-Beranger, P. Perreau, O. Weber, I. Ben-Akkez*, A. Cros*, A. Bajolet*, S. Haendler*, P. Fonteneau*, P. Gouraud*, E. Richard*, F. Abbate*, D. Barge*, D. Pellissier-Tanon*, B. Dumont*, F. Andrieu, J. Passieux*, R. Bon*, V. Barral, D. Golanski*, D. Petit*, N. Planes*, O. Bonin**, W. Schwarzenbach**, T. Poiroux, O. Faynot, M. Haond*, F. Boeuf*, CEA-LETI, MINATEC, *STMicroelectronics, **SOITEC

For the first time, CMOS devices on UTBOX 25nm combined with strained SOI (sSOI) substrates have been demonstrated. A 20% Ion boost is highlighted with these substrates compared to the standard UTBB SOI ones. Performance up to 1530µA/µm @ Ioff=100nA/µm (Vd 1V) for a nominal Lg=30nm with a CET of 1.5nm for the NMOS has been achieved. The viability of this substrate has been demonstrated thanks to our hybrid process, through threshold voltage modulation and leakage current reduction, with back biasing for short devices. In addition, cell current improvement of 23% in 0.12µm2 bitcell is noticed for sSOI at the same stand-by current vs the standard UTBB SOI. Finally, the functionality of hybrid ESD device underneath the BOX is demonstrated.

13.5 - 5:05 p.m.

Strain Engineered Extremely Thin SOI (ETSOI) for High-Performance CMOS, A. Khakifirooz, K. Cheng, T. Nagumo*, N. Loubet**, T. Adam, A. Reznicek, J. Kuss, D. Shahrjerdi, R. Sreenivasan, S. Ponoth, H. He, P. Kulkarni, Q. Liu**, P. Hashemi^#, P. Khare**, S. Luning^, S. Mehta, J. Gimbert**, Y. Zhu^#, Z. Zhu^##, J. Li, A. Madan^##, T. Levin, F. Monsieur**, T. Yamamoto*, S. Naczas, S. Schmitz, S. Holmes, C. Aulnette^, N. Daval^, W. Schwarzenbach^, B-Y. Nguyen^, V. Parachuri, M. Khare, G. Shahidi^#, B. Doris, IBM Research, *Renesas, **STMicroelectronics, ^GLOBALFOUNDRIES, ^^SOITEC, ^#IBM TJ Watson Research Center, ^##IBM SRDC

High-performance strain-engineered ETSOI devices are reported. Three methods to boost the performance, namely contact strain, strained SOI (SSDOI) for NFET, and SiGe-on-insulator (SGOI) for PFET are examined. Significant performance boost is demonstrated with competitive drive currents of 1.65mA/µm and 1.25mA/µm and effective currents of 0.95mA/µm and 0.70mA/µm at Ioff =100nA/µm and VDD of 1V, for NFET and PFET, respectively.