Session 14 – TAPA 3

Novel Passive and Active BEOL Technologies

Wednesday, June 13, 3:25 p.m.

Chairs: R. Klein, AMD

H. Morimura, NTT Microsystem Integration Lab

14.1 - 3:25 p.m.

A Novel Chemically, Thermally and Electrically Robust Cu Interconnect Structure with an Organic Non-porous Ultralow-k Dielectric Fluorocarbon (k=2.2), X. Gu, A. Teramoto, R. Kuroda, Y. Tomita, T. Nemoto, S.-i. Kuroki, S. Sugawa, T. Ohmi, Tohoku University

A novel chemically, thermally and electrically robust Cu damascene interconnects with an organic non-porous ultralow-k (ULK) dielectric fluorocarbon (k=2.2), deposited by an advanced microwave excited plasma enhanced CVD, is demonstrated. A practical nitrogen plasma treatment (NPT) was employed to minimize chemically damage introduction to fluorocarbon in post-etching cleaning and CMP processes. Also, a new structure with a delamination-protective-liner (DPL), instead of barrier-metal, between Cu and fluorocarbon is introduced to avoid thermally induced electrical degradation and to reduce the interconnect delay significantly (by >30% in 32 nm-node). Non-porous ULK fluorocarbon with NPT and DPL technologies is a promising candidate for high performance Cu interconnects.

14.2 - 3:50 p.m.

Graphene Interconnect Lifetime Under High Current Stress, X. Chen, D. Seo*, S. Seo**, H. Chung*, H.-S.P. Wong, Stanford University, *Samsung Advanced Institute of Technology, **Sejong University

Lifetime of multi-layer graphene interconnects under constant current stress is studied for the first time. Under a stress current density of 20MA/cm2 at 250⁰C exposed to air, Mean-Time-To-Fail (MTTF) of uncapped CVD graphene wire is about 6 hours. It is shown that lifetime is mainly limited by defect formation due to graphene oxidation.

14.3 - 4:15 p.m.

Operation of Functional Circuit Elements using BEOL-Transistor with InGaZnO Channel for On-chip High/Low Voltage Bridging I/Os and High-Current Switches, K. Kaneko, H. Sunamura, M. Narihiro, S. Saito, N. Furutake, M. Hane, Y. Hayashi, Renesas Electronics Corporation

Functional circuit elements based on novel BEOL-transistors with a wide-band-gap oxide semiconductor InGaZnO (IGZO) film are integrated onto LSI Cu-interconnects, and their operations are demonstrated. High-current comb-type transistors show excellent Ion/Ioff ratio (>108) and high-Vd operation with linear area dependence, realizing area-saving compact high-current BEOL switches. Successful operation of voltage-controlled inverter switches with high-Vd enables on-chip bridging I/Os between high/low voltage on conventional Si system LSIs. Setting the gate-to-drain offset design to just 0.1m realizes +20V enhancement of the breakdown voltage to ~60V with excellent safety operation at around Vd=50V due to the wide-band-gap characteristics.

14.4 - 4:40 p.m.

High Performance Bilayer Oxide Transistor for Gate Driver Circuitry Implemented on Power Electronic Devices, S. Jeon, H. Kim, H. Choi, I. Song, S.-E. Ahn, C.J. Kim, J. Shin, U.-I. Chung, I. Yoo, K. Kim, Samsung Electronics Co.

The integration of electronically active oxide transistors onto silicon circuits represents an innovative approach to improving the performance of devices. In this paper, we present high performance oxide transistors for use as gate drive circuitry integrated on top of a power electronic device, providing a novel power system. With this approach, we aim to reduce the form factor, cost, weight and noise of power management integrated circuitry (PMIC). Specifically, as a core device component in gate driver, oxide transistor exhibits remarkable performance such as, high mobility (23~47cm2/Vs) and high breakdown voltages of 60~340V despite low process temperatures (<300°C). In addition, we demonstrate the dynamic behavior of the inverter and the latch produced by oxide transistor and thus a complete and functioning gate drive circuitry can be implemented on top of PMIC as depicted in this report. We also discuss carrier transport mechanism of bi-layer oxide transistor through the assessment of low frequency noise property, which gives a further insight in the underlying physics of oxide transistor.

14.5 - 5:05 p.m.

Sub-fM DNA Sensitivity by Self-Aligned Maskless Thin-Film Transistor-Based SoC Bioelectronics, M.-C. Chen, C.-H. Lin, C.-Y. Lin, F.-K. Hsueh, W.-H. Huang, Y.-C. Lien, H.-C. Chen, H.-T. Hsueh*, C.-W. Huang*, C.-T. Lin*, Y.-C. Liu**, T.-H. Lee**, M.-Y. Hua, J.-T. Qiu, M.-C. Liu, Y.-J. Lee, J.-M. Shieh, C. Ho, C. Hu^, F.-L. Yang, National Nano Device Laboratories, *National Taiwan University, **Chang Gung University, University of California, Berkeley

This is the first study to successfully achieve record DNA sensitivity (sub-fM) by self-aligned, maskless, dual-channel, and metal-gate-based thin-film transistor nano-wire FET. Both novel device architecture (dual-channel) and optimization of integration processes (microcrystalline silicon and self-aligned sidewall sub-50 nm critical dimension) of nano-wire FET enhance the sensitivity to biological entities substantially. Meanwhile, the proposed device is accomplished with an embedded VLSI CMOS circuit. It can thus offer high application potential to pH, protein, and DNA probing in SoC-based portable bioelectronics.