Session 15 – TAPA 2

CMOS Platform

Thursday, June 14, 8:05 a.m.

Chairs: W. Maszara, Globalfoundries

S. Inaba, Toshiba Corp.

15.1 - 8:05 a.m.

High Performance Bulk Planar 20nm CMOS Technology for Low Power Mobile Applications, H. Shang, S. Jain, E. Josse*, E. Alptekin, M.H. Nam**, S.W. Kim^, K.H. Cho^, I. Kim^, Y. Liu**, X. Yang**, X. Wu**, J. Ciavatti**, N.S. Kim**, R. Vega, L. Kang**, H.V. Meer**, S. Samavedam**, M. Celik*, S. Soss**, H. Utomo, R. Ramachandran, W. Lai, V. Sardesai, C. Tran, J.Y. Kim^, Y.H. Park^, W.L. Tan**, T. Shimizu^^, R. Joy**, J. Strane, K. Tabakman, F. Lalanne*, P. Montanini*, K. Babich**, J.B. Kim^, L. Economikos, W. Cote, C. Reddy**, M. Belyansky, R. Arndt, U. Kwon, K. Wong, D. Koli**, D. Leveakis, J.W. Lee^, J. Muncy, S. Krishnan, D. Schepis, X. Chen, B.D. Kim^, C. Tian, B.P. Linder, E. Cartier, V. Narayanan, G. Northrop, O. Menut*, J. Meiring, A. Tomas, M. Aminpur, S.H. Park^, K.Y. Weybright, R. Mann**, A. Mittal**, M. Eller#, S. Lian^, R. Divakaruni, S. Bukofsky, J.D. Kim^, J. Sudijono**, W. Neumueller#, F. Matsuoka^^, R. Sampson*, IBM Microelectronics, *STMicroelectronics, **GLOBALFOUNDRIES, ^Samsung Electronics, ^^Toshiba Corporation, #IMC GmbH

In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive current up to 2X 28nm at equivalent leakage is achieved through co-optimization of HKMG process and strain engineering. A fully functional, high-density (0.081um2 bit-cell) SRAM is reported with a corresponding Static Noise Margin (SNM) of 160mV at 0.9V. An advanced patterning and metallization scheme based on ULK dielectrics enables high density wiring with competitive R-C.

15.2 - 8:30 a.m.

A 22nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, Self-Aligned Contacts and High Density MIM Capacitors, C. Auth, C. Allen, A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarmane, T. Ghani, T. Glassman, R. Grover, W. Han, D. Hanken, M. Hattendorf, P. Hentges, R. Heussner, J. Hicks, D. Ingerly, P. Jain, S. Jaloviar, R. James, D. Jones, J. Jopling, S. Joshi, C. Kenyun, H. Liu, R. McFadden, B. McIntyre, J. Neirynck, C. Parker, L. Pipes, I. Post, S. Pradhan, M. Prince, S. Ramey, T. Reynolds, J. Roester, J. Sanford, J. Seiple, P. Smith, C. Thomas, D. Towner, T. Troeger, G. Weber, P. Yashar, K. Zawadzki, K. Mistry, Intel Corp.

A 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time. These transistors feature a 3rd-generation high-k + metal-gate technology and a 5th generation of channel strain techniques resulting in the highest drive currents yet reported for NMOS and PMOS. The use of tri-gate transistors provides steep subthreshold slopes (~70mV/dec) and very low DIBL (~50mV/V). Self-aligned contacts are implemented to eliminate restrictive contact to gate registration requirements. Interconnects feature 9 metal layers with ultra-low-k dielectrics throughout the interconnect stack. High density MIM capacitors using a hafnium based high-k dielectric are provided. The technology is in high volume manufacturing.

15.3 - 8:55 a.m.

28nm FDSOI Technology Platform for High-Speed Low-Voltage Digital Applications, N. Planes, O.Weber*, V. Barral*, S. Haendler, D. Noblet, D. Croain, M. Bocat, P.-O. Sassoulas, X. Federspiel, A. Cros, A. Bajolet, E. Richard, B. Dumont, P. Perreau*, D. Petit, D. Golanski, C. Fenouillet-Beranger*, N. Guillot, M. Rafik, V. Huard, S. Puget, X. Montagner, M.-A. Jaud*, O. Rozeau*, O. Saxod, F. Wacquant, F. Monsier, D. Barge, L. Pinzelli, M. Mellier, F. Boeuf, F. Arnaud, M. Haond, STMicroelectronics, *CEA-LETI, MINATEC

For the first time, a full platform using FDSOI technology is presented. This work demonstrates 32% and 84% speed boost at 1.0V and 0.6V respectively, without adding process complexity compared to standard bulk technology. We show how memory access time can be significantly reduced thanks to high Iread, by keeping competitive leakage values. Yield of ~14Mb SRAM cells is demonstrated, allowing to measure for the first time Vmin of SRAM arrays.

15.4 - 9:20 a.m.

Advanced Modeling and Optimization of High Performance 32nm HKMG SOI CMOS for RF/Analog SoC Applications, S. Lee, J. Johnson, B. Greene, A. Chou, K. Zhao, M. Chowdhury, J. Sim, A. Kumar, D. Kim, A. Sutton, S.H. Ku, Y. Liang, Y. Wang, D. Slisher, K. Duncan, P. Hyde, R. Thoma, J. Deng, Y. Deng, R. Rupani, R. Williams, L. Wagner, C. Wermer, H. Li, B. Johnson, D. Daley, J.O. Plouchart, S. Narasimha, C. Putnam, E. Maciejewski, W. Henson, S. Springer, IBM Semiconductor Research and Development Center

We demonstrate advanced modeling and optimization of 32nm high-K metal gate (HKMG) SOI CMOS technology for high-speed digital and RF/analog system-on-chip applications. To enable high-performance RF/analog circuit design, we present challenging device modeling features and their enhancements. At nominal Lpoly, floating-body NFET and PFET demonstrate peak fT of 300GHz and fMAX of higher than 350GHz with excellent model-to-hardware accuracy. For precision analog circuit design, body-contacted (BC) FETs and various passives are offered, and their performance and modeling accuracy are co-optimized to push the technology limit and achieve state-of-the-art circuits, e.g., 28Gb/s serial link transceiver and LC-tank VCO operating at higher than 100GHz.