Session 17 – TAPA 2

Technology / Circuits Joint Focus Session – Design in Scaled Technologies

Thursday, June 14, 10:00 a.m.

Chairs: J. Cheek, Freescale

R. Takemura, Hitachi, Ltd.

17.1 – 10:00 a.m.

Design Enablement at 14nm: The Challenge of Being Early, Accurate, and Complete (Invited), M.E. Mason, Texas Instruments

Progress evidenced by Moore’s Law has driven increased performance at decreased cost per function. Often, the price of this progress is balanced against complexity and time-to-market (both directly impacting cost). Design enablement teams must mitigate these cost factors by delivering accurate process design kits (PDKs) that predict both process and device performance at production on a schedule that supports time-to-market goals. Here, we examine some key technology issues affecting the critical relationship between process, device, design and products.

17.2 – 10:25 a.m.

Designing in Scaled Technologies: 32nm and Beyond (Invited), S. Kosonocky, T. Burd, K. Kasprak, R. Schultz, R. Stephay, AMD

VLSI technology scaling in the 32-nm node and beyond has presented designers with increasing challenges to obtain performance gains, power and area reductions each successive generation. Maximum voltage limits, decreasing interconnect performance and reliability, and device changes have forced designers to rethink system and circuit design for enhanced system performance and improved user experience. This paper will review some of the challenges and potential solutions to designing in advanced nodes including bias temperature instabilities (BTI), time-dependent dielectric breakdown (TDDB), metal pitch scaling limitations, electro-migration, and challenges designing with next generation CMOS devices.

17.3 – 10:50 a.m.

The Optimum Device Parameters for High RF and Analog/MS Performance in Planar MOSFET and FinFET (Invited) T. Ohguro, Y. Higashi, K. Okano, S. Inaba, Y. Toyoshima, Toshiba

For analog and RF designer, higher fT, fmax and low flicker noise are attractive to realize the high performance circuit. The scaled planar MOSFET has lead to the higher operation frequency application. Recently, un-doped double gate MOSFETs, such as FinFET are promising candidates for scaling CMOS into the sub-32nm node and below because of its good cut-off characteristics and better scalability due to double gate mode operation. However, reported figure of merit of FinFET are lower than planar MOSFET [3, 4]. In this paper, we discuss device parameter to obtain high RF performance for planar MOSFET and FinFET. Additionally, structural merits of FinFET relative to flicker noise are discussed.

17.4 – 11:15 a.m.

Dynamic Intrinsic Chip ID Using 32nm High-K/Metal Gate SOI Embedded DRAM, D. Fainstein, S. Rosenblatt, A. Cestero, N. Robson, T. Kirihata, S.S. Iyer, IBM Systems and Technology Group

A random intrinsic chip ID method generates a pair of 4Kb binary strings using retention fails in 32nm SOI embedded DRAM. Hardware results show ID overlap distance mean=0.58 and σ=0.76 and demonstrate 100% authentication for 346 chips. The analytical model predicts > 99.999% unique IDs for 10^6 parts.

17.5 – 11:40 a.m.

A Fully-Digital Phase-Locked Low Dropout Regulator in 32nm CMOS, A. Raychowdhury, D. Somasekhar, J. Tschanze, V. De, Intel Corp.

A fully-digital phase-locked low dropout regulator (LDO) has been designed in 32nm CMOS for fine-grained power delivery to multi-Vcc digital circuits. Measurements across a wide range of input voltages and currents exhibit that the LDO offers excellent load regulation and efficiency close to 97% of ideal efficiency at nominal load current conditions (ILOAD=3mA).