Session 18 – TAPA 3

RRAM II

Thursday, June 14, 10:00 a.m.

Chairs: G. Jurczak, IMEC

Y. Nakao, Rohm Co., Ltd.

18.1 - 10:00 a.m.

Integration of 4F2 Selector-less Crossbar Array 2Mb ReRAM Based on Transition Metal Oxides for High Density Memory Applications, H.D. Lee, S.G. Kim, K. Cho, H. Hwang, H. Choi, J. Lee, S.H. Lee, H.J. Lee, J. Suh, S.-O. Chung, Y.S. Kim, K.S. Kim, W.S. Nam, J.T. Cheong, J.T. Kim, S. Chae, E.-R. Hwang, S.N. Park, Y.S. Sohn, C.G. Lee, H.S. Shin, K.J. Lee, K. Hong, H.G. Jeong, K.M. Rho, Y.K. Kim, S. Chung, J. Nickel, J.J. Yang, H.S. Cho, F. Perner, R.S. Williams, J.H. Lee, S.K. Park, S.-J. Hong, Hynix Semiconductor Inc.

4F2 selector-less crossbar array 2Mb ReRAM test chip with 54nm technology has been successfully integrated for high cell efficiency and high density memory applications by implementing parts of decoders to row/column lines directly under the cell area. Read/write specifications for memory operation in a chip are presented by minimizing sneak current through unselected cells. The characteristics of memory cell (nonlinearity, Kw >8, Iop <10uA, Vop <3V), TiOx/Ta2O5, are modified for its working in a chip by adopting appropriate materials for a resistor stack and spacer. Write condition in a chip makes a critical impact on read margin and read/write operation in a chip has been verified.

18.2 - 10:25 a.m.

Multi-Layer Sidewall WO_X Resistive Memory Suitable for 3D ReRAM, W.C. Chien, F.M. Lee, Y.Y. Lin, M.H. Lee, S.H. Chen, C.C. Hsieh, E.K. Lai, H.H. Hui, Y.K. Huang, C.C. Yu, C.F. Chen, H.L. Lung, K.Y. Hsieh, C.-Y. Lu, Macronix International Co., Ltd.

An easy to fabricate, low-cost, multi-layer sidewall WOX ReRAM device is proposed for 3D ReRAM application. A 2-layer (10nm x 100nm) device is fabricated and characterized for the first time. The WOX is grown by conventional RTO process but a special semi-permeable TiN (SP-TiN) is developed to achieve the necessary extrusion-free structure for 3D ReRAM. The multi-layer sidewall WOX ReRAM devices show characteristics similar to planar devices, but the reasons for layer-to-layer variation and some performance degradation still need to be understood.

18.3 - 10:50 a.m.

Ultrathin (<10nm) Nb₂O₅/NbO₂ Hybrid Memory with Both Memory and Selector Characteristics for High Density 3D Vertically Stackable RRAM Applications, S. Kim, X. Liu, J. Park, S. Jung, W. Lee, J. Woo, J. Shin, G. Choi, C. Cho, S. Park, D. Lee, E.-j. Cha, B.-H. Lee, H.D. Lee, S.G. Kim, S. Jung, H. Hwang, Gwangju Institute of Science and Technology, *Hynix Semiconductor Inc.

We report, for the first time, the novel concept of ultrathin (~10nm) W/NbOx/Pt device with both threshold switching (TS) and memory switching (MS) characteristics. Excellent TS characteristics of NbO2, such as high temperature stability (~160oC), fast switching speed (~22ns), good switching uniformity, and extreme scalability of device area (φ~10nm)/thickness (~10nm) were obtained. By oxidizing NbO2, we can form ultrathin Nb2O5/NbO2 stack layer for hybrid memory devices with both TS and MS. Without additional selector device, 1Kb cross-point hybrid memory device without SET/RESET disturbance up to 106 cycles was demonstrated.

18.4 - 11:15 a.m.

Process-Improved RRAM Cell Performance and Reliability and Paving the Way for Manufacturability and Scalability for High Density Memory Application, G.S. Kar, A. Fantini, Y.Y. Chen, V. Paraschiv, B. Govorean, H. Hody, N. Jossart, H. Tielens, S. Brus, O. Richard, T. Vandeweyer, D. Wouters, L. Altimime, M. Jurczak, imec

Here for the first time we discuss RRAM cell performance and reliability through process improvement. Excellent post-cycling (1E6) retention and post-bake retention and endurance have been achieved for the optimized process conditions. The optimized RRAM cells show potential for manufacturability and scalability for high density memory application.

18.5 - 11:40 a.m.

Ultralow Sub-500nA Operating Current High-Performance TiN\Al₂O₃\HfO₂\Hf\TiN Bipolar RRAM Achieved Through Understanding-Based Stack-Engineering, L. Goux, A. Fantini, G. Kar, Y.-Y. Chen, N. Jossart, R. Degraeve, S. Clima, B. Govoreanu, G. Lorenzo, G. Pourtois, D.J. Wouters, J.A. Kittl, L. Altimime, M. Jurczak, imec

We demonstrate sub-500nA switching and tunable set voltage by inserting thin Al2O3 layer in TiN\HfO2\Hf\TiN RRAM cell. Stack engineering clearly led to novel insights into the switching phenomenology: (i) O-scavenging is key in the forming process and stack-asymmetry management; (ii) dielectric-stack thinning allows lower forming current; (iii) ‘natural’ (asymmetry-induced) reset switching takes place close to the TiN anode; (iv) reset resistance is limited by material-barrier properties at TiN interface