Session 19 – TAPA 2

High Mobility – Ge Devices

Thursday, June 14, 1:30 p.m.

Chairs: T. Ernst, CEA-LETI, MINATEC

T. Tanaka, Fujitsu Semiconductor

19.1 - 1:30pm

High Mobility Ge pMOSFETs with 0.7 nm Ultrathin EOT using HfO₂/Al₂O₃/GeO_x/Ge Gate Stacks Fabricated by Plasma Post Oxidation, R. Zhang, P.-C. Huang, N. Taoka, M. Takenaka, S. Takagi, University of Tokyo

HfO2/Al2O3/GeOx/Ge gate stacks were fabricated by applying the plasma post oxidation to HfO2/Al2O3/Ge structures. These Ge gate stack are shown to simultaneously realize both ultrathin EOT of ~0.7 nm and low Dit of 1011 cm-2eV-1 order. The superior operation of (100) Ge pMOSFETs with these gate stacks has been demonstrated with record high hole mobility of 596 cm2/Vs under ~0.8 nm EOT among the Ge pMOSFETs reported so far.

19.2 - 1:55pm

85nm-Wide 1.5mA/µm-I_ON IFQW SiGe-pFET: Raised vs Embedded Si_0.75Ge_0.25S/D Benchmarking and In-Depth Hole Transport Study, J. Mitard, L. Witters, G. Eneman, G. Hellings, L. Pantisano, A. Hikavyy, R. Loo, P. Eyben, N. Horiguchi, A. Thean, Imec

Beside the VTH-tunability, we found that a raised SiGe S/D module offers higher LG-scalability than an embedded SiGe S/D in SiGe-IFQW pFETs. An in-depth transport study of record performing 1.5mA/μm-ION 85x35nm2 strained-SiGe Implant Free Quantum Well (IFQW) pFETs reveals that mobility improvement is still the key performance booster whereas LG-scaling has finally a limited impact.

19.3 - 2:20pm

High-Mobility and Low-parasitic Resistance Characteristics in Strained Ge Nanowire pMOSFETs with Metal Source/Drain Structure Formed by Doping-free Processes, K. Ikeda, M. Ono, D. Kosemura*, K. Usuda, M. Oda, Y. Kamimuta, T. Irisawa, Y. Moriyama, A. Ogura, T. Tezuka, AIST, *Meiji University

Metal source/drain (S/D) Ge nanowire MOSFETs with a compressive strain as high as 3.8% were fabricated by the 2-step Ge-condensation technique without intentional doping for the S/D. Record high inversion hole mobility ( 855 cm2/Vs @ Ns = 5e12cm-2) and saturation drain current 731uA/um at Vd=-1V were achieved among Ge nanowire pFETs ever reported. It is found that the extremely low contact resistivity ~ 4e-8 ohm-cm2 for the Schottky contact contributes to the high saturation current as well as the high mobility.

19.4 - 2:45 p.m.

Segmented-Channel Si_1-xGe_x/Si pMOSFET for Improved I_ON and Reduced Variability, B. Ho, N. Xu, B. Wood*, V. Tran*, S. Chopra*, Y. Kim*, B.-Y. Nguyen**, O. Bonnin**, C. Mazure**, S. Kuppurao*, C.-P. Chang*, T.-J. King Liu, University of California, Berkeley, *Applied Materials, **SOITEC

Segmented-channel Si(1-x)Ge(x)/Si pMOSFETs are fabricated using a conventional process, starting with a corrugated Si(1-x)Ge(x)/Si substrate. As compared with control devices fabricated using the same process but starting with a non-corrugated Si(1-x)Ge(x)/Si substrate, the segmented-channel MOSFETs show better layout efficiency (30% higher ION for IOFF=10 nA per µm layout width) due to enhanced hole mobility, and dramatically reduced dependence of performance on layout width due to the geometrical regularity of the channel region.