Session 2 – TAPA 2

Advanced Fin FET Devices and Technology

Tuesday, June 12, 10:25 a.m.

Chairs: G. Yeap, Qualcomm

M. Masahara, Nat’l Institute of AIST

2.1 - 10:25 a.m.

10nm-Diameter Tri-Gate Silicon Nanowire MOSFETs with Enhanced High-Field Transport and V_th Tunability through Thin BOX, M. Saitoh, K. Ota, C. Tanaka, K. Uchida*, T. Numata, Toshiba Corp., *Tokyo Institute of Technology

We demonstrate high-performance 10nm-diameter tri-gate nanowire transistors (NW Tr.) with Vth tunability, small variability and negligible self-heating. Optimized S/D and stress memorization technique (SMT) lead to significant parasitic resistance reduction and mobility enhancement. Saturation velocity increase by SMT further enhances high-field carrier velocity and Ion of 1mA/um at Ioff of 100nA/um is achieved. We also demonstrate Vth control in tri-gate NW Tr. with thin BOX for the first time. The degradation of body effect by NW narrowing can be recovered by thinning NW height, enabling dynamic power and performance management.

2.2 - 10:50a.m.

Strain-Induced Performance Enhancement of Tri-Gate and Omega-Gate Nanowire FETs Scaled Down to 10nm Width, R. Coquand*, M. Cassé, S. Barraud, P. Leroux, D. Cooper, C. Vizioz, C. Comboroure*, P. Perreau, V. Maffini-Alvaro, C. Tabone, L. Tostie, F. Allain S. Barnola, V. Delaye, F. Aussenac, G. Reimbold, G. Ghibaudo**, D. Munteanu, S. Monfray*, F. Boeuf, O. Faynot, T. Poiroux,CEA-LETI, MINATEC, *STMicroelectronics, **IMEP-LAHC

A detailed study of performance in uniaxially-strained Si nanowire (NW) transistors fabricated by lateral strain relaxation of biaxial SSOI substrate is presented. 2D strain imaging demonstrates the lateral strain relaxation resulting from nanoscale patterning. For the first time, an improvement of electron mobility in SSOI NW scaled down to 10nm width has been successfully demonstrated (+55% with respect to SOI NW). This improvement is maintained even by using H2 annealing used for Omega-Gate. On short gate length, a strain-induced Ion gain as high as 40% at LG=45nm is achieved for multiple-NWs active pattern.

2.3 - 11:15a.m.

Channel Doping Impact on FinFETs for 22nm and Beyond, C.-H. Lin, R. Kambhampati*, R. Miller*, T. Hook, A. Bryant, W. Haensch, P. Oldiges, I. Lauer, T. Yamashita, V. Basker, T. Standaert, K. Rim, E. Leobandung, H. Bu, M. Khare, IBM Research Division, *GLOBALFOUNDRIES

The natural choice to achieve multiple threshold voltages (Vth) in fully-depleted devices is by choosing the appropriate gate workfunction for each device. However, this comes at the cost of significantly higher process complexity. The absence of a body contact in FinFETs and insensitivity to back-gate bias leaves the conventional channel doping approach as the most practical technique to achieve multiple Vth. This choice, however, introduces a variable that is usually not considered in the context of fully depleted devices. For the first time, we demonstrate a multiple Vth solution at relevant device geometries and gate pitch for the 22nm node. We investigated the impact of FinFET channel doping on relevant device parameters such as Tinv, mobility, electrostatic control and Vth mismatch. We also show that Vth extraction by the “constant current” method could mislead the DIBL analysis of devices with greatly different channel mobility.

2.4 - 11:40 a.m.

FinFET Parasitic Resistance Reduction by Segregating Shallow Sb, Ge and As Implants at the Silicide Interface, C. Kenney, K.-W. Ang, K. Matthews, M. Liehr, M. Minakais, M. Rodgers*, V. Kaushik*, S. Novak*, S. Gausepohl*, C. Hobbs, P. Kirsch, R. Jammy, J. Pater, SEMATECH, *CNSE State University of New York

A new contact technology comprising antimony (Sb) co-implantation and segregation to reduce Schottky barrier height (SBH) and parasitic series resistance for N-FinFETs is reported. Experiments with shallow Sb, Ge and As co-implantation in the source/drain (S/D) regions of SOI FinFET structures found that all three implant species significantly reduced extrinsic resistance. The Sb implant with a 5e13 cm-2 dose produced the best results with a 31% reduction of extrinsic resistance and a corresponding Ion increases of 19%. This optimum Sb implant is shown to reduce specific contact resistivity (ρc) by decreasing the SBH and increasing the barrier steepness. Electrostatic control comparable to the reference device indicates no degradation in short channel effects for either Sb, Ge or As.