Session 20 - TAPA 3

3D Integration Technology

Thursday, June 14, 1:30 p.m.

Chairs: A. Antonelli, Novellus Systems, Inc.

T. Tanaka, Tohoku Univ.

20.1 - 1:30 p.m.

Ultrafast Parallel Reconfiguration of 3D-Stacked Reconfigurable Spin Logic Chip with On-chip SPRAM (SPin-transfer torque RAM), T. Tanaka, H. Kino, R. Nakazawa, K. Kiyoyama*, H. Ohno, M. Koyanagi, Tohoku University, *Nagasaki Institute of Applied Science

We have developed novel 3D-stacked reconfigurable spin logic chip having ultrafast on-chip SPRAM to overcome drawbacks of conventional reconfigurable LSIs. Two reconfigurable spin logic chips were carefully designed and successfully stacked using 3D integration technology. From the SPRAM cell evaluation, the fastest write speed of 5 ns was obtained in the circuits. To realize higher performance reconfigurable LSIs, parallel reconfiguration was fully demonstrated for the stacked reconfigurable spin logic chips for the first time. Both ultrafast on-chip SPRAM and 3D-stacked structure will open a new era of reconfigurable LSIs.

20.2 - 1:55 p.m.

Development of Ultra-Thin Chip-on-Wafer Process Using Bumpless Interconnects for Three-Dimensional Memory/Logic Applications, N. Maeda, H.Kitada, K. Fujimoto**, Y. Kim, S.Kodama*, S.Yoshimi**, M. Akazawa**, Y. Mizushima^, T. Ohba, University of Tokyo, *DISCO Corporation, **Dai Nippon Printing, ^Fujitsu Laboratory Ltd.

Chip-on-Wafer (COW) stacking structure using stack-first and bumpless interconnects was successfully fabricated for the first time. Chips were arrayed and bonded onto the wafer by back-to-face and gap filling between chips were carried out using organic material without void formation. Chips on the wafer were thinned down to 5 µm. Via-holes were formed at off-chip area (outside the chip). Copper redistribution line was formed using the via-first Damascene method. Lower leakage current as low as back ground was found between pads. No failure and an approximate 100% yield were achieved in the vertical wiring for multi-chips COW stacking.

20.3 - 2:20 p.m.

High-Aspect Ratio Through Silicon Via (TSV) Technology, H.-P. Chang, H.-Y. Chen, P.-C. Kuo, A. Chien, E. Liao, T.-C. Lin, J. Wei, Y.-C. Lin, Y.-H. Chen, K.-F. Yang, H.-A. Teng, J. Tsai, Y.C. Tseng, S.Y. Chen, C.-C. Hsieh, M.F. CHEN, Y.-H. Liou, T.-J. Wu, S. Y. Hou, W.-C. Chiou, S.-P. Jeng, C.-H.Yu, Taiwan Semiconductor Manufacturing Company, Ltd.

The density of through-silicon-via (TSV) on CMOS chip is limited by TSVdimension and keep-out zone (KOZ). A high aspect ratio Cu TSV process, 2 mmx 30 mm, is demonstrated on 28nm CMOS baseline with good electricalperformance and low cost. By implementing 2 mm x 30 mm TSV, the Si stressin the vicinity of TSV caused by thermal expansion is able to be relieved.It is, therefore, shown that the relaxation of TSV stress is correlatedwith minimized keep-out zone (KOZ). The achievement of excellentperformance of 3D-IC yield and high aspect ratio TSV embedded devicecharacteristics are key milestones in the promising manufacturability of3D-IC by silicon foundry technology.

20.4 - 2:45 p.m.

Demonstration of Inter-chip Data Transmission in a Three-dimensional Stacked Chip Fabricated by Chip-level TSV Integration, K. Hozawa, F. Furuta, Y. Hanaoka, M. Aoki, K. Osada, K. Takeda, K.W. Lee*, T. Fukushima*, M. Koyanagi*, ASET, *Tohoku University

Successful 3D integration of a stacked chip fabricated by a “chip-level through-silicon-via (TSV)” process was confirmed by inter-chip data transmission. According to measurements of the electrical properties of the stacked chip, structural design of TSV contact wiring is very important for chip-level/via-last TSV integration. That is, the design influences TSV contact resistance, TSV coupling capacitance, and wiring capacitance of the surrounding Cu/low-k interconnections.