Session 21 – TAPA 2

Scaled III-V Transistors and Modeling

Thursday, June 14, 3:25 p.m.

Chairs: J. Kavalieros, Intel Corp.

B.H. Lee, Gwangju Institute of Sci. and Tech.

21.1 - 3:25 p.m.

Sub-60 nm Deeply-Scaled Channel Length Extremely-thin Body In_xGa_1-xAs-On-Insulator MOSFETs on a Si with Ni-InGaAs Metal S/D and MOS Interface Buffer Engineering, S. Kim, M. Yokoyama, N. Taoka, R. Nakane, T. Yasuda*, O. Ichikawa**, N. Fukuhara**, M. Hata**, M. Takenaka, S. Takagi, University of Tokyo, *National Institute of Advanced Industrial Science and Technology, **Sumitomo Chemical Co., Ltd.

We report the first demonstration of sub-60 nm deeply-scaled InGaAs- and InAs-on-insulator MOSFETs on Si substrates with MOS interface buffer engineering and Ni-InGaAs metal source/drain (S/D). The devices provide 400 % I_on enhancement, when comparing to that of an In_0.53Ga_0.47As control device with the same drain-induced-barrier-lowering (DIBL) of 100 mV/V, which is attributable to the mobility enhancement and the S/D parasitic resistance (R_SD) reduction. In addition, InAs-OI MOSFETs with the MOS interface buffer show excellent electrostatic characteristics. A MOSFET with channel length (L_ch) of 55 nm shows small DIBL of 84 mV/V and subthreshold slope (S.S.) of 105 mV/dec, both of which do not significantly degrade with a decrease of L_ch, because of the extremely-thin channel thickness.

21.2 - 3:50 p.m.

InAs Quantum-Well MOSFET (L_g = 100 nm) with Record High g_m, f_T and f_max, T.-W. Kim, R. Hill, C.D. Young, D. Veksler, L. Morassi*, S. Oktybrshky**, J. Oh, C.Y. Kang, D.-H. Kim^, J.A. Del Alamo^^, C. Hobbs, P. Kirsch, R. Jammy, SEMATECH, *University of Modena and Emilia, **CNSE, ^Teledyne, ^^Massachusetts Institute of Technology

This paper reports InAs quantum-well (QW) MOSFETs with record transconductance (gm,max = 1.73 mS/μm) and high-frequency performance (fT = 245 GHz and fmax = 355 GHz) at Lg = 100 nm. This record performance is achieved by using a low Dit composite Al2O3/InP gate stack, optimized layer design and a high mobility InAs channel.

21.3 - 4:15 p.m.

Antimonide NMOSFET with Source Side Injection Velocity of 2.7x10⁷ cm/s for Low Power High Performance Logic Applications, A. Ali, H. Madan, M. Barth, M. Hollander, B. Boos*, B. Bennett*, S. Datta, The Pennsylvania State University, *Naval Research LAb

Antimonide (Sb) quantum well (QW) MOSFETs are demonstrated with integrated high-k dielectric (1nmAl2O3-10nm HfO2). The long channel Sb NMOS exhibits effective electron mobility of 6,000 cm2/Vs at high field (2 x 1012 /cm2 of charge density (Ns)), which is the highest reported value for any III-V MOSFET. The short channel Sb NMOSFET (LG = 150nm) exhibits a cut-off frequency (fT) of 120GHz, fT - LG product of 18GHz.µm and source side injection velocity (veff) of 2.7x107 cm/s, at drain bias (VDS) of 0.75V and gate overdrive of 0.6V. The measured fT and fT x LG are 2 x higher, and veff is 4x higher than Si NMOS (1.0-1.2V VDD) at similar LG, and are the highest for any III-V MOSFET.

21.4 - 4:40 p.m.

Understanding the Feasibility of Scaled III-V TFET for Logic By Bridging Atomistic Simulations and Experimental Results, U.E. Avci, S. Hasan, D.E. Nikonov, R. Rios, K. Kuhn, I.A. Young, Intel Corporation

A detailed comparison between III-V TFET’s experimental characteristics and atomistic quantum mechanical predictions is reported to study the validity of the performance improvement predictions of a scaled TFET. Simulations did not employ any fitting parameters to match the experimental data, but instead used material and geometry parameters as the only inputs. The results show that the experimental and simulation characteristics are in reasonable agreement, suggesting that the experimental devices are without significant unknown effects or defects, and the atomistic simulations have good predictability. The differences between scaled TFET predictions and large experimental TFET devices are shown to be due to the geometry, meaning that improved electrostatics with thin body and double-gate is required for TFET scaling. Results demonstrate that the III-V TFET is a realistic candidate for future low-voltage logic applications.

21.5 - 5:05 p.m.

InGaSb: Single Channel Solution for Realizing III-V CMOS, Z. Yuan, A. Nainani*, A. Kumar, X. Guan, B. R. Bennett**, J.B. Boos**, M.G. Ancona**, K.C. Saraswat, Stanford University, *Applied Materials, **Naval Research Lab

There has been an upsurge of interest in the possibility of a low-power, high-performance CMOS based on III-V materials. For such a technology to be realized, advances are needed in a number of areas including: (a) comparable high performance from n- and p-channel devices for complementary logic; (b) reducing the impact of Dit; and (c) overcoming low density of states (DOS) of electrons which could limit the NMOS ION. In this study, methods are investigated that deliver improvements in these three areas. We chose to work on the 6.1-6.2Å lattice constant system with InGaSb as the channel material because of its advantages in terms of band engineering and high mobility/offsets for both electrons and holes. Despite its larger lattice constant, antimonide’s are also found to be potentially more suitable for hetero-integration. We demonstrate electron/hole mobility > 4000/900cm2/Vs can be achieved in a single channel material. For the first time in III-V systems, both n- and p-channel transistors with one single channel material show comparable high on-current.