Session 22 – TAPA 3

Variability Characterization and Modeling

Thursday, June 14, 3:25 p.m.

Chairs: T. Skotnicki, STMicroelectronics

N. Sugii, Hitachi, Ltd.

22.1 - 3:25 p.m.

Threshold Voltage and DIBL Variability Modeling for SRAM and Analog MOSFETs, N. Damrongplasit, L. Zamudio*, S. Balasubramanian*, University of California, Berkeley, *GLOBALFOUNDRIES

A physically-based variability model is developed to explain threshold voltage (VT) and drain induced barrier lowering (DIBL) variations, and their correlations. Inputs to the model rely on forward (F) and reverse (R) data of measured transistor pair mismatch. Positionally asymmetric and symmetric random dopant fluctuation components of VT and DIBL variability are identified for SRAMs and analog devices from a 32nm HKMG technology and their correlations explained.

22.2 - 3:50 p.m.

The Understanding of the Trap Induced Variation in Bulk Tri-Gate Devices by a Novel Random Trap Profiling (RTP) Technique, H.M. Tsai, E.R. Hsieh*, S.S. Chung, C.H. Tsai, R.M. Huang*, C.T. Tsai*, C.W. Liang*, National Chiao Tung University, *United Microelectronics Corporation

Not only the popular random dopant fluctuation (RDF), but also the traps, caused by the HC stress or NBTI-stress, induce the Vth variations. To identify these traps, for the first time, a unique random trap profiling feasible for 3D device applications has been demonstrated on trigate devices. For such devices, the oxide traps are generated not only near the drain side but also on the sidewall, after hot carrier(HC) and NBTI stresses. More importantly, the Vth variation in pMOSFET under NBTI becomes much worse as a result of an additional surface roughness effect. This method provides us a valuable tool for the diagnosis of reliability in 3D devices (e.g., FinFET).

22.3 - 4:15 p.m.

Accurate Chip Leakage Prediction: Challenges and Solutions, X. Yu, J. Deng, S. Loo, K. Dezfulian, S. Lichtensteiger*, J. Bickford*, N. Habib*, P. Chang, A. Mocuta, K. Rim, IBM SRDC, *IBM System and Technology Group

A systematic method is proposed to address modeling challenges in accurate chip level leakage prediction, namely a precise total leakage width count method, a simple model to quantify leakage uplift caused by systematic across-chip variation, and a consistent model to capture 3-sigma leakage and leakage spread at fixed performance.