Session 3 – TAPA 2

NAND Flash

Tuesday, June 12, 10:25 a.m.

Chairs: J. Alsmeier, SanDisk

H.-T. Lue, Macronix International Co, Ltd.

3.1 - 10:25 a.m.

A New Metal Control Gate Last Process (MCGL Process) for High Performance DC-SF (Dual Control Gate with Surrounding Floating Gate) 3D NAND Flash Memory, Y. Noh, Y. Ahn, H. Yoo, B. Han, S. Chung, K. Shim, K. Lee, S. Kwak, S.Shin, I. Choi, S. Nam, G. Cho, D. Sheen, S. Pyi, J. Choi, S. Park, J. Kim, S. Lee, S. Aritome, S. Hong, S. Park, Hynix Semiconductor Inc.

A new Metal Control Gate Last process (MCGL process) has been successfully developed for the DC-SF (Dual Control gate with Surrounding Floating gate cell)[1] three-dimensional (3D) NAND flash memory. The MCGL process can realize a low resistive tungsten (W) metal word-line with high-k IPD, a low damage on tunnel oxide/IPD, and a preferable FG shape.

And also, a conventional bulk erase can be used, replaced GIDL erase in BiCS[3][4], due to direct connection between channel poly and p-well by the channel contact holes. Therefore, by using MCGL process, high performance and high reliability of DC-SF cell can be achieved for MLC/TLC 256Gb/512Gb 3D NAND flash memories

3.2 - 10:50 a.m.

Intrinsic Fluctuations in Vertical NAND Flash Memories, E. Nowak, J.-H. Kim, H.Y. Kwon, Y.-G. Kim, J.S. Sim, S.-H. Lim, D.S. Kim, K.-H. Lee, Y.-K. Park, J.-H. Choi, C. Chung, Samsung Electronics Co. Ltd.

Vertical NAND (VNAND) technology relies on polysilicon for channel material. Two intrinsic variation sources of the cell threshold voltage induced by polysilicon traps have been identified and simulated: Random Trap Fluctuation (RTF) and Random Telegraph Noise (RTN). We demonstrate that RTN is enhanced by the polysilicon material and an original model explains the asymmetric RTN distribution observed after endurance. This work enables the prediction of VT distribution for VNAND devices in MLC operation.

3.3 - 11:15 a.m.

A New GIDL Phenomenon by Field Effect of Neighboring Cell Transistors and its Control Solutions in Sub-30 nm NAND Flash Devices, I.H. Park, W.-G. Hahn, K.-W. Song, K.H. Choi, H.-K. Choi, S.B. Lee, C.-S. Lee, J.H. Song, J.M. Han, K.H. Kyoung, Y.-H. Jun, Samsung Electronics

Gate induced drain leakage (GIDL) is one of the major mechanism which degrades program disturbances in NAND flash operations. In this study, we have observed GIDL phenomenon in scaled NAND string, such as the location or the mechanism related with band-to-band-tunneling generation, are quite different from conventional ones in sub-30 nm technologies due to the short distance between neighboring cells and lightly doped S/D region. By device simulation, we have found that the GIDL current of NAND is strongly influenced by 5-terminal biasing condition of adjacent cells and hence should be described by 5-terminal field effect model instead of conventional 3-terminal model. By silicon measurements (with a 27-nm NAND product), we have confirmed the confidence of the proposed model. The proposed model is expected to provide an important clue for making inhibit control solutions against program disturbance in sub-30 nm NAND flash devices.

3.4 - 11:40 a.m.

Ferroelectricity in HfO₂ Enables Nonvolatile Data Storage in 28 nm HKMG, J. Müller, E. Yurchuk*, T. Schlösser**, J. Paul, R. Hoffmann, S. Müller*, D. Martin*, S. Slesazeck*, P. Polakowski, J. Sundqvist, M. Czernohorsky, K. Seidel, P. Kücher, R. Boschke**, M. Trentzsch**, K. Gebauer**, U. Schröder*, T. Mikolajick*, Fraunhofer Center Nanoelectronic Technologies, *NaMLab GmbH, **GLOBALFOUNDRIES

Even though researched for several decades, the ferroelectric field effect transistor (FeFET) based on traditional perovskite-based ferroelectrics like PZT or SBT still has fundamental shortcomings. Its potential, however, remains unchallenged. Unlike the current-based STT-MRAM, RRAM, PCRAM and Flash technologies the ferroelectric approach is based on a field effect and consumes the lowest power during switching. Scalability and manufacturability on the other hand still remain a major issue when utilizing perovskite-based ferroelectrics. With the ability to engineer ferroelectricity in the well-known and fully CMOS-compatible HfO2 based dielectrics we are able to report, that the two order of magnitude scaling gap, prevailing ever since the introduction of FeFETs, has been closed at the 28 nm node. The world´s most aggressively scaled FeFETs were successfully fabricated using ferroelectric Si:HfO2 in a 28 nm HKMG stack (TiN/Si:HfO2/SiO2/Si). Excellent yield, fast switching, good retention and endurance will be demonstrated.