Session 4 – TAPA 1

High-K / Metal Gate Scaling

Tuesday, June 12, 1:30 p.m.

Chairs: T.-J. King Liu, Univ. of California, Berkeley

Y. Akasaka, Tokyo Electron Taiwan, Ltd.

4.1 - 1:30 p.m.

Implementing Cubic-Phase HfO₂ with K-Value ~ 30 in Low-V_T Replacement Gate pMOS Devices for Improved EOT-Scaling and Reliability, L.-Å. Ragnarsson, C. Adelmann, Y. Higuchi, K. Opsomer, A. Veloso, S.A. Chew, E. Röhr, E. Vecchio, X. Shi, K. Devriendt, F. Sebaai, T. Kauerauf, M. Pawlak, T. Schram, S. Van Elshocht, N. Horiguchi, A. Thean, Imec

Higher k-value HfO2 (k~30) was evaluated in replacement metal gate pMOS devices. The higher-k was achieved by doping and anneal of the HfO2 causing crystallization into the cubic phase. The resulting gate-stack has up to 1000 x lower gate-leakage current compared to a reference HfO2: JG at -1 V is 2 µA/cm2 at EOT~9.7 Å. The better JG – EOT-scaling, result in performance and reliability improvements when normalized to the JG.

4.2 - 1:55 p.m.

A Novel Low Resistance Gate Fill for Extreme Gate Length Scaling at 20nm and Beyond for Gate-Last High-k/Metal Gate CMOS Technology, U. Kwon, K. Wong, S. Krishnan, L. Economikos, X. Zhang*, C. Ortolland, L.D. Thanh*, J.-B. Laloe*, J.Y. Huang*, L. Edge, H.M. Wang*, M. Gribelyuk, D. Rath*, R. Bingert**, Y. Liu*, R. Bao, I. Kim^, R. Ramachandran, W. Lai, J. Cutler, D.S. Salvador*, Y. Zhang*, J. Muncy, B. Paruchuri^^, M. Krishnan^#, V. Narayanan^#, R. Divakaruni, X. Cheng, M. Chudzik, IBM Microelectronics Division, *GLOBALFOUNDRIES, Inc., **STMicroelectronics, ^Samsung Electronics, ^^IBM Research, ^#IBM TJ Watson Research Center

Replacement metal gate (RMG) process requires gate fill with low resistance materials on top of work function tuning metals. Conventional titanium (Ti)-aluminum (Al) based RMG metal fill scheme for low resistance gate formation becomes challenging with further gate length scaling for 20nm node and beyond. In this work, we have demonstrated competitive low resistance gate formation at smaller than 25nm Lgate using a novel cobalt (Co)-aluminum based metal fill scheme for extreme gate length scaling. Challenges in CMP for the implementation as well as assessment on resistance and device characteristics of this new low resistance fill scheme are also discussed.

4.3 - 2:20 p.m.

Dramatic Improvement of High-K Gate Dielectric Reliability by Using Mono-Layer Graphene Gate Electrode, J.K. Park, S.M. Song, J.H. Mun, B.J. Cho, KAIST

We demonstrate for the first time that the high-k gate dielectric reliability is dramatically improved by replacing metal gate electrode with graphene gate electrode. The atomic-scale thickness and flexible nature of graphene completely eliminate mechanical stress in the high-k gate dielectric, resulting in significant reduction of trap generation in the high-k film. Almost all the electrical properties related to reliability of MOSFET such as the PBTI, TDDB, leakage current, etc are significantly improved. Data retention and program/erase properties of charge trap Flash memory are also greatly improved.

4.4 - 2:45 p.m.

Process Control & Integration Options of RMG Technology for Aggressively Scaled Devices, A. Veloso, Y. Higuchi, S. Chew, K. Devriendt, L. Ragnarsson, F. Sebaai, T. Schram, S. Brus, E. Vecchio, K. Kellens, E. Röhr, G. Eneman, E. Simoen, M. Cho, V. Paraschiv, Y. Crabbe, X. Shi, H. Tielens, A. Van Ammel, H. Dekkers, P. Favia, J. Geypen, H. Bender, A. Phatak*, J. Del Agua Borniquel*, K. Xu*, M. Allen*, C. Liu*, T. Xu*, W. Yoo**, A. Thean, N. Horiguchi, IMEC, *Applied Materials, **WaferMasters Inc.

We report on aggressively scaled RMG-HKL devices, with tight low-VT distributions [29mV sigma(VTsat) for PMOS, 49mV sigma(VTsat) for NMOS at 35nm Lgate] achieved through controlled EWF-metal alloying for NMOS, and providing an in-depth overview of its enabling features: 1) physical mechanisms, model supported by TCAD simulations and analysis techniques such as TEM, EDS; 2) process optimizations implementation: oxygen sources reduction, control of RF-PVD TiAl/TiN ratio and reduced Hgate, also impacting stress induced in the channel. Additional key features: 1) Al vs. W as fill-metal, with careful liner/barrier materials selection and tuning yielding well-behaved devices with tight Rgate distributions down to 20nm Lgate, and enabling both PMOS and NMOS low-VT values for high aspect-ratio gates (60nm Hgate, Lgate down to 30nm); 2) wet-etch vs. siconi clean for dummy-dielectric removal, with HfO2 post-deposition N2-anneal resulting in substantial BTI improvement without EOT or low-field/peak mobility penalty, and good noise response.