Session 6 – TAPA 1
Low Power and Steep Subthreshold Technology
Tuesday, June 12, 3:25 p.m.
Chairs: A.
Seabaugh, Notre Dame Univ.
T.
Iwamatsu, Renesas Electronics Corp.
6.1 – 3:25 p.m.
Recent Progress and Challenges for Relay Logic Switch Technology (Invited), T.-J.
King Liu, L. Hutin, I-R. Chen, R. Nathanael, Y. Chen, E. Alon, University of California, Berkeley
The energy efficiency of CMOS technology is fundamentally limited by
transistor off-state leakage (Ioff). Mechanical
switches have zero Ioff and therefore could be
advantageous for ultra-low-power digital logic applications. This paper
discusses recent advancements in relay logic switch technology and current
challenges which must be addressed to realize its promise.
6.2 – 3:50 p.m.
III-V Field Effect Transistors for Future Ultra-Low
Power Applications (Invited), G. Dewey, B.C. Kung, R. Kotlyar,
M. Metz, N. Mukherjee, M. Radosavljevic, Intel Corp.
This paper
summarizes the electrostatics and performance of III-V field effect transistors
including thin body planar MOSFETs, 3-D tri-gate MOSFETs, and Tunneling FETs
(TFETs). The electrostatics of the III-V devices is shown to improve from thick
body planar to thin body planar and then to 3-D tri-gate. Beyond the MOSFET
structures, sub-threshold slope (SS) steeper than 60
mV/decade has been demonstrated in III-V TFETs. These III-V devices,
especially the 3-D tri-gate MOSFET and TFET, are viable options for future
ultra low power applications.
6.3 – 4:15 p.m.
Steep-Slope Tunnel Field-Effect Transistors Using
III-V Nanowires/Si Heterojunction (Invited), K. Tomioka, M. Yoshimura, T. Fukui, Hokkaido
University
In this paper, we report on a tunneling field-effect transistors
(TFETs) using III-V nanowire (NW)/Si heterojunctions. We experimentally demonstrate steep
turn-on behaviors using the TFET with surrounding-gate architecture and high-k dielectrics. Adjusting series
resistances in this device structure is important for achieving steep-slope
switching. A minimum subthreshold slope (SS) of the
TFET is 21 mV/dec (VDS of 0.10 – 1.00 V)
at room temperature.
6.4
– 4:40 p.m.
Strained
Tunnel FETs with Record Ion:First Demonstration of ETSOI TFETs with SiGe Channel
and RSD, A.
Villalon, C. Le Royer, M. Cassé, D. Cooper, B. Prévitali, C. Tabone, J.-M.
Hartmann, P. Perreau, P. Rivallin, J.-F. Damlencourt, F. Allain, F. Andrieu, O.
Weber, O. Faynot, T. Poiroux, CEA, LETI, Minatec
We present for the first time Tunnel FETs (TFETs) obtained
with a FDSOI CMOS process flow featuring High-K Metal Gate, ultrathin body
compressively strained SiGe (Ge content from 0 to 30%) based channels, and
SiGe30% Raised SD. We analyse the tunnelling improvements due to the different
technological injection boosters: ultrathin body & EOT, strain, low band
gap source, and low temperature SD anneal. For the first time, TFETs with large
ON current (up to 428µA/µm) are demonstrated (with >x1000 ION gain vs. SOI
reference).
6.5 – 5:05
p.m.
Demonstration
of Improved Heteroepitaxy, Scaled Gate Stack and Reduced Interface States
Enabling Heterojunction Tunnel FETs with High Drive Current and High On-Off
Ratio, D. Mohata, B.
Rajamohanan, Y. Zhu*, M. Hudait*, R. Southwick*, Z. Chbili**, D. Gundlach**, J.
Suehle**, J. Fastenau^, D. Loubychev^, A. Liu^, T. Mayer, V. Narayanan, S.
Datta, The Pennsylvania State University, *Virginia Tech, **NIST, ^IQE Inc.
Staggered tunnel junction (GaAs0.35Sb0.65 /In0.7Ga0.3As) is
used to demonstrate heterojunction tunnel FET (TFET) with the highest drive
current, Ion, of 135µA/µm and highest Ion/Ioff ratio of 2.7104
(Vds=0.5V, Von-Voff=1.5V). Effective oxide thickness (EOT) scaling (using
Al2O3/HfO2 bilayer gate stack) coupled with pulsed I-V measurements
(suppressing Dit response) enable demonstration of steeper switching TFET.