Session 7 – TAPA 2

STT MRAM

Tuesday, June 12, 3:25 p.m.

Chairs: E. Kan, Cornell Univ.

S. Hong, Hynix Semiconductor, Inc.

7.1 - 3:25 p.m.

Enhancement of Data Retention and Write Current Scaling for Sub-20nm STT-MRAM by Utilizing Dual Interfaces for Perpendicular Magnetic Anisotropy, J.-H. Park, Y. Kim, W. Lim, J. Kim, S. Park, J. Kim, W. Kim, K. Kim, J. Jeong, K.S. Kim, H. Kim, Y.J. Lee, S. Oh, J.E. Lee, S.O. Park, S. Watts*, D. Apalkov*, V. Nikitin*, M. Krounbi*, S. Jeong, S. Choi, H. Kang, C. Chung, Samsung Electronics Co., Ltd., *Grandis Inc.

We investigate the sub-20nm level scalability of STT-MRAM cells possessing perpendicular magnetization induced from the interface of free layer (FL) and MgO tunnel barrier. We demonstrate that the MTJs utilizing dual interfaces of FL and MgO exhibit enhanced scalability with high thermal stability and low switching current, compared with the MTJs with a single interface. As thermal stability factor (delta) varies as a function of MTJ dimension, MTJs with dual interfaces show over 60 at 20nm node, while MTJs of single interface show around 33. MTJs with dual interface also exhibit lower switching current per thermal stability (Ic/delta), ~1/2 level of single interface MTJs.

7.2 - 3:50 p.m.

Demonstration of Non-Volatile Working Memory Through Interface Engineering in STT-MRAM, C. Yoshida, T. Ochiai, Y. Iba, Y. Yamazaki, K. Tsunoda, A. Takahashi, T. Sugii, LEAP

We engineered the interface of the MgO barrier prepared by post-oxidation of Mg metal to improve structural and electronic properties of magnetic tunnel junctions (MTJs). Drastic improvements in magnetoresistance ratio (MR) and critical switching voltage (Vc) with low resistance area product (RA) were achieved by inserting CoFe seed layer under the oxidized barrier. The MTJ satisfied over 1016 write cycles at 10 ns pulse under the operation voltage of 0.65 V. From these results, we have verified for the first time the hypothesis that a spin transfer torque magnetoresistance random access memory (STT-MRAM) is suitable for a non-volatile working memory.

7.3 - 4:15 p.m.

High-speed and Reliable Domain Wall Motion Device: Material Design for Embedded Memory and Logic Application, S. Fukami, M. Yamanouchi, T. Koyama*, K. Ueda*, Y. Yoshimura*, K.J. Kim*, D. Chiba*, H. Honjo**, N. Sakimura**, R. Nebashi**, Y. Kato**, Y. Tsuji**, A. Morioka**, K. Kinoshita, S. Miura**, T. Suzuki^, H. Tanigawa^, S. Ikeda, T. Sugibayashi**, N. Kasai, T. Ono, H. Ohno, Tohoku University, *Kyoto University, **NEC Corp., ^Renesas Electronics Corp.

High-speed capability and excellent reliability of a magnetic domain wall (DW) motion device required for high-speed embedded memory and logic-in-memory applications were achieved by optimizing the film stack structure of Co/Ni wire. Low-current with high-speed writing, high heat resistance, low error rate, wide operation range for temperature and magnetic field, high retention, and high endurance features were confirmed. The developed technology here makes an ultra-low-power system LSI possible.

7.4 - 4:40 p.m.

Spintronics Primitive Gate with High Error Correction Efficiency 6 (P_error)² for Logic-in Memory Architecture, Y. Tsuji, R. Nebashi, N. Sakimura, A. Morioka, H. Honjo, K. Tokutome, S. Miura, T. Suzuki*, S. Fukami*, K. Kinoshita^, T. Hanyu^, T. Endo^, N. Kasai^, H. Ohno^, T. Sugibayashi, NEC Corp., *Renesas Electronics Corp., ^Tohoku University

A spintronics primitive gate with redundancy was designed using domain wall motion (DWM) cells, and the data-missing rate was drastically improved to ~ 6 (Perror)^2 when the error rate per DWM cell was (Perror). All the DW motion cells aligned in series were written simultaneously, which suppressed the increase in power consumption when writing. Application of 4-terminal DWM cells with physically separated current paths for writing and reading saved extra path transistors for redundancy and there were no area overheads.

7.5 - 5:05 p.m.

Highly Scalable STT-MRAM with 3-Dimensional Cell Structure Using In-plane Magnetic Anisotropy Materials, S. Lee, K. Kim, K. Kim, U. Pi, Y. Jang, U.-I. Chung, I. Yoo, K. Kim, SAIT

Novel spin transfer torque MRAM cells with three dimensional freelayer structures were suggested for the high density memory below 20nm technology node. By folding the freelayer to a special geometry, the 3D MTJ Cell structure retains large freelayer volume without an increase of cell foot-print, scaling down the MRAM cells even with in-plane magnetic anisotropy materials. From the micromagnetic calculation with Nudged Elastic Band (NEB) method, we confirmed the thermal stability over 60 in 3D MTJ cell with 15ⅹ30nm2 area.