Session 9 – TAPA 2

Process Technology

Wednesday, June 13, 10:25 a.m.

Chairs: C.-P. Chang, Applied Materials

K. Miyashita,Toshiba Corp.

9.1 - 10:25 a.m.

Atom Probe Tomography for 3D-Dopant Analysis in FinFET Devices, A.K. Kambham, G. Zschaetzsch, Y. Sasaki, M. Togo, N. Horiguchi, J. Mody, A. Florakis, D.R. Gajula*, A. Kumar, M. Gilbert, W. Vandervorst, imec, *Gueen’s University of Belfast

As the nano scale device performance depends on the detailed engineering of the dopant distribution, advanced doping processes are required. Progressing towards 3D-structures like FinFETs, studying the dopant gate overlap and conformality of doping calls for metrology with 3D-resolution and the ability to confine the analyzed volume to a small 3D-structure. We demonstrate that through an appropriate methodology this is feasible using Atom Probe Tomography (APT). We extract the 3D-dopant profile and important parameters such as gate overlap and profile steepness, from transistor formed with plasma doping processes. Analyzing samples with different doping processes, the APT results are entirely consistent with device performances (Ioff vs. Ion).

9.2 - 10:50 a.m.

A 32nm High-K and Metal-Gate Anti-Fuse Array Featuring a 1.01µm² 1T1C Bit Cell, S. Kulkarni, S. Pae, Z. Chen, W. Hafez, B. Pedersen, A. Rahman, T. Tong, U. Bhattacharya, C.-H. Jan, K. Zhang, Intel Corporation

A 1 k-bit high-density OTP (One Time Programmable)-ROM array featuring a new anti-fuse memory is presented using 32nm high-k (HK) and metal-gate (MG) CMOS process. Our 32nm HK+MG SOC process technology enables smallest reported one-transistor one-capacitor (1T1C) bit cell area measuring 1.01µm2. The 32-row by 32-column array with a programmable sensing scheme demonstrates yield exceeding 99.9% and robust reliability.

9.3 - 11:15 a.m.

Replacement Metal Gate Extendible to 11 nm Technology, N. Yoshida, X. Fu, K. Xu, Y. Lei, H. Yang, S. Sun, H. Chen, A. Darlak, R. Donohoe, C. Lazik, R. Jakkaraju, A. Noori, S. Hung, I. Peidous, C.-P. Chang, A. Brand, Applied Materials

This paper describes Co-Al metal fill capable of filling sub-10nm trenches. Co-Al fill shows no degradation of threshold voltage (VTH) variation. The conductivity of the fill was evaluated using a Co-Al alloy conductance model. Co-Al shows extendibility to 11nm by the superior conductivity and gap fill.

9.4 - 11:40 a.m.

ZnO: An Attractive Option for n-Type Metal-Interfacial Layer-Semiconductor (Si, Ge, SiC) Contacts, P. Paramahans Manik, S. Gupta*, R.Mishra, N. Agarwal, A. Nainani*, Y.-C. Huang*, M. Abraham*, S. Kapadia, U. Ganguly, S. Lodha, Indian Institute of Technology Bombay, *Applied Materials Inc.

We propose ZnO as a highly attractive interfacial layer (IL) option for n-type metal-IL-semiconductor (Si, Ge, SiC) MIS contacts because of (i) good conduction band alignment between ZnO and Si/Ge/SiC, (ii) high n-type doping possible in ZnO, and, (iii) low Fermi-level pinning factor for metal/ZnO contacts. Device simulations suggest better scalability for MIS contacts versus silicides/germanides for future FinFET technologies. Contact diode measurements on Ti/n+ZnO/n-Ge and Ti/n+ZnO/n-Si devices show nearly 1000x increase in current densities due to the presence of an n+-ZnO IL. In comparison to alternate IL options such as Al2O3 and TiO2, n+-ZnO gives significantly higher current densities on n-Ge as demonstrated through device simulations and experimental data. Specific contact resistivity of 1x10-6 Ω cm2 is demonstrated through circular TLM devices fabricated on n+-Ge (1x1019 cm-3) substrates using n+ZnO IL.