Session 4-1

A 14-Gb/s 32 mW AC Coupled Receiver in 90-nm CMOS

 

Abstract

This paper introduces a high-speed AC coupled receiver architecture for high density interconnects. The proposed architecture combines a novel hysteresis circuit path and a linear broadband amplifier path to recover a NRZ signal from an 80-fF capacitively coupled channel. Using this dual path technique, a 90-nm CMOS prototype achieves 14-Gb/s operation while consuming 32 mW from a 1.2-V supply. The measured sensitivity of the receiver is better than 100 mVp-p differential.