Session 8A-2

Will Strain be Useful for 10nm Quasi-BallisticFDSOI Devices?
An Experimental Study

 

Abstract

For the first time, we have extracted the ballisticity rates of strained and unstrained n-Fully Depleted Silicon On Insulator devices with gate lengths down to 10nm. Thanks to a new fully experimental extraction methodology taking into account multi-subband population, we demonstrate that strain takes actively part in quasi-ballistic drain current improvement thanks to a 22 percent injection velocity enhancement, which will become the predominant transport parameter for the next generation of CMOS devices. In addition, we find that strained channel ballisticity rates are slightly greater than unstrained ones whatever the considered temperature and gate length. This rate improvement can be closely related to the mobility gain for short channel architectures.