2000 VLSI Technology Short Course

Tapa I/II

Key Technologies for 130-100nm Generations

 

Monday, June 12, 8:30 a.m.

Organizers:

    Simon Wong, Stanford University
    Seiichiro Kawamura, Fujitsu Ltd.

 

8:25 a.m. Introduction

 

8:30 a.m. Design Issues,

Harry Veendrick, Philips Research Labs

 

10:00 a.m. Break

 

10:15 a.m. Transistor Technologies:

  • Gate Stack Process, Masaaki Niwa, Matsushita

  • Shallow Junction Process, Bunji Mizuno, Matsushita

 

11:45 p.m. Lunch

 

1:15 p.m. Lithography,

Hiroshi Ohtsuka, ASET/Oki

 

2:45 p.m. Break

 

3:00 p.m. Interconnect

Bob Havemann, SEMATECH

 

4:30 p.m. Conclusion

 

 

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