Session 13-3

A 8-Gbps Low-Latency Multi-Drop On-Chip Transmission
Line Interconnect with 1.2-mW Two- Way Transceivers

 

Abstract

This paper proposes a multi-drop on-chip transmission line interconnect for high-speed on-chip buses. The proposed two-way transceiver serves as both Tx and Rx for on-chip transmission lines and can branch signals without delay degradation. The proposed interconnect, which has six two-way transceivers and 5-mm-long transmission line, performs 8 Gbps signaling with power dissipation of 7.1 mW.