Session 7A-1
A Low-Power Multi-Gate FET CMOS Technology with 13.9ps
Inverter Delay,
Large-Scale Integrated High Performance Digital Circuits
and SRAM
Abstract
| This paper presents an in-depth analysis of digital performance of a Multi-Gate FET technology. Ring oscillators with metal gates and undoped fins show an inverter delay of 13.9ps at 1V, the highest per-formance of a Multi-Gate FET technology reported at 1.9nA off-current/stage. NAND and NOR show significant improvement in de-lay vs. stack height compared to bulk CMOS. SRAM cells and prod-uct-typical critical paths with more than 10k transistors demonstrate the capability for large-scale integration. |