Press Kit
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The following press materials are available for pre-conference publicity for the 2015 Symposia on VLSI Technology & Circuits
Press Releases
- VLSI Symposia 2015 lead release (English) - April 20, 2015
- VLSI Symposia 2015 Technical Tip Sheet (English) - April 20, 2015
- VLSI Symposia 2015 lead release (Japanese) - April 20, 2015
- VLSI Symposia 2015 Technical Tip Sheet (Japanese) - April 20, 2015
- VLSI Symposia 2015 lead release (Chinese) - April 20, 2015
- VLSI Symposia 2015 Technical Tip Sheet (Chinese) - April 20, 2015
- VLSI Symposia 2015 lead release (Korean) - April 20, 2015
- VLSI Symposia 2015 Technical Tip Sheet (Korean) - April 20, 2015
Images
- VLSI Technology Symposium 2015 logo (.jpg)
- VLSI Circuit Symposium 2015 logo (.jpg)
- Paper T2-1, A 14 nm SoC Platform Technology Featuring 2nd Generation Tri-Gate Transistors, 70 nm Gate Pitch, 52 nm Metal Pitch, and 0.0499 um2 SRAM Cells, Optimized for Low Power, High Performance and High Density SoC Products (.jpg)
- Paper T2-2, Highly Reliable TaOx ReRAM with Centralized Filament for 28-nm Embedded Application (.jpg)
- Paper T2-3, High-Mobility High-Ge-Content Si1-xGex-OI PMOS FinFETs with Fins Formed Using 3D Germanium Condensation with Ge Fraction up to x~ 0.7, Scaled EOT~8.5Å and ~10nm Fin Width (.tif)
- Paper T2-4, Design and Demonstration of Reliability-Aware Ge Gate Stacks with 0.5 nm EOT (.jpg)
- Paper T3-4, 15-nm Channel Length MoS2 FETs with Single- and Double-Gate Structures (.jpg)
- Paper T7-1, 2.8-GB/s-Write and 670-MB/s-Erase Operations of a 3D Vertical Chain-Cell-Type Phase-Change-Memory Array (.jpg)
- Paper T8-3, Resistivity of Copper Interconnects Beyond the 7 nm Node (.jpg)
- Paper T13-3, Confined Epitaxial Lateral Overgrowth (CELO): A Novel Concept for Scalable Integration of CMOS-Compatible InGaAs-on-Insulator MOSFETs on Large-Area Si Substrates (.pdf)
- Paper T15-1, High-Performance Low-Leakage Enhancement-Mode High-K Dielectric GaN MOS-HEMTs for Energy-Efficient, Compact Voltage Regulators and RF Power Amplifiers for Low-Power Mobile SoCs (.jpg)
- Paper JFS3-4, Holistic Technology Optimization and Key Enablers for 7nm Mobile SoC (.jpg)
- Paper JFS4-1, Active-Lite Interposer for 2.5 & 3D Integration (.jpg)
- Paper C4-2, A 0.66e-rms Temporal-Readout-Noise 3D-Stacked CMOS Image Sensor with Conditional Correlated Multiple Sampling (CCMS) Technique (.jpg)
- Paper C4-5, A 3D Stacked CMOS Image Sensor with 16Mpixel Global-Shutter Mode and 2Mpixel 10000fps Mode Using 4 Million Interconnections (.jpg)
- Paper C6-1, A 16-Channel Wireless Neural Interfacing SoC with RF-Powered Energy-Replenishing Adiabatic Stimulation (.jpg)
- Paper C12-2, A 6.4Gb/s/pin at Sub-1V Supply Voltage TX-Interleaving Technique for Mobile DRAM Interface (.jpg)
- Paper C13-2, A 10.6mm3 Fully-Integrated, Wireless Sensor Node with 8GHz UWB Transmitter (.jpg)
- Paper C15-2, A 40-Gb/s 9.2-mW CMOS Equalizer (.jpg)
- Paper C19-5, 1.8 Mbit/mm2 Ternary-CAM Macro with 484 ps Search Access Time in 16 nm Fin-FET Bulk CMOS Technology (.jpg)
- Paper C21-2, A 13-ENOB, 5 MHz BW, 3.16 mW Multi-Bit Continuous-Time ΔΣ ADC in 28 nm CMOS with Excess-Loop-Delay Compensation Embedded in SAR Quantizer (.jpg)
- Paper C22-3, A 60GHz Wireless Transceiver Employing Hybrid Analog/Digital Beamforming with Interference Suppression for Multiuser Gigabit/s Radio Access (.jpg)
- Paper C23-1, Broadwell : A Family of IA 14nm Processors (.jpg)
- Paper C23-5, Resonant Clock Mega-Mesh for the IBM z13™ (.jpg)
Press Registration
Registration at the 2015 Symposia on VLSI Technology & Circuits is complimentary for the press. If you plan to attend, please download the press registration form, and fax or mail the completed one to the VLSI Secretariat (Japan and Asia) at vlsisymp[at]ics-inc.co.jp. Please prepare to show a business card when you arrive at the Symposia.
If you have any registration/attendance questions, please contact the Secretariat.
Editor Contact
Whether you would like to do a news story, conference preview or an in-depth exploration of a particular technology, please contact the Publicity chairs or the Secretariat for additional information or interviews you may need.
Shinya Yamakawa
JFE Technology Publicity Chair
shinya.yamakawa[at]jp.sony.com
Makoto Ikeda
JFE Circuits Publicity Chair
ikeda[at]silicon.u-tokyo.ac.jp